Memory Tiering by Access Activity Across DRAM and CXL

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Solution Overview

Problem

Existing storage systems face inefficiencies due to varying latencies in accessing different types of storage devices, with high-latency devices like CXL memory being less expensive but offering limited capacity, while low-latency devices like DRAM are more costly and have limited capacity.

Innovation Solution

Implementing a memory tiering system that organizes storage media in a hierarchy based on latency, promoting frequently accessed data to higher tiers (like DRAM) and demoting infrequently accessed data to lower tiers (like CXL memory), with operations managed in user space to enhance customization and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If data is stored in high-latency storage devices like CXL memory, then cost is reduced and capacity is increased, but access latency increases

Engineering Contradiction:
Improveaccess latencyVSAvoidstorage capacity
Core Design Contradiction:
Loss of timeVSQuantity of substance

Solution Approach 1:

The storage system is segmented into multiple tiers with different performance and cost characteristics. Hot data is stored in high-performance storage devices while cold data is stored in high-capacity, low-cost devices like CXL memory. This segmentation allows the system to optimize for both speed and capacity by placing data in appropriate tiers based on access patterns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension to storage organization, creating a multi-tier architecture where data can be placed at different levels based on access frequency. This dimensional approach allows simultaneous optimization for both fast access (upper tiers) and high capacity (lower tiers).

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If data is stored in low-latency storage devices like DRAM, then access speed is improved, but cost increases and capacity is limited

Engineering Contradiction:
Improveaccess speedVSAvoidstorage capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

Different parts of the storage system are assigned different qualities based on local needs. Frequently accessed data resides in high-speed storage devices for optimal performance, while less frequently accessed data is placed in lower-speed, higher-capacity devices. This local quality approach ensures that speed is optimized where needed while capacity is maximized elsewhere.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The storage tiering is dynamic rather than static. The system continuously monitors access patterns and automatically migrates data between tiers based on changing demands. This dynamic adjustment allows the system to adapt to varying workload requirements and optimize the balance between speed and capacity over time.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12481588B2Systems and methods for memory representation and management
Publication Date: 2025.11.25 SAMSUNG ELECTRONICS CO LTD
  • US12481588B2 patent drawing
  • US12481588B2 patent drawing
  • US12481588B2 patent drawing

AI summary

Systems and methods for memory representation and management are disclosed. A request to allocate memory in a first storage medium is identified. The first storage medium may be associated with a first tier of a memory hierarchy. The memory may be represented via at least a first node of a first data structure in response to the request. The first data structure may be associated with the first tier. Activity associated with a memory address represented by the first node may be tracked, and an order for the first node in the first data structure may be updated based on the activity. An association of the first node may be moved from the first data structure to a second data structure. The second data structure may be associated with a second tier of the memory hierarchy.