Memory Tile Access Patterns for Disturb Management
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Solution Overview
Problem
Cross-point arrays in memory tiles suffer from disturb effects, such as threshold recovery and coupling effects, which limit the efficiency and performance of memory devices by requiring transitions between memory tiles, leading to increased overhead and energy consumption.
Innovation Solution
Implementing a selection and access sequence that allows consecutive selections and accesses within a single memory tile using a nonadjacent pattern, such as a diagonal pattern, to manage disturb effects and enable high-performance operations while minimizing latency and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory access methods are used in cross-point arrays, then memory operations can be performed, but disturb effects such as threshold recovery and coupling effects occur, limiting efficiency and performance
Solution Approach 1:
The memory array is divided into multiple memory tiles, each independently selectable. This segmentation allows the system to confine access operations to specific tiles, preventing disturb effects from propagating across the entire array and enabling more efficient access patterns within individual tiles.
Solution Approach 2:
The patent implements dynamic selection of memory tiles based on access patterns. By dynamically determining which tiles to access and in what sequence, the system optimizes performance while minimizing disturb effects, adapting to different operational requirements in real-time.
2Object-affected harmful factors
If transitions between memory tiles are required to manage disturb effects, then disturb effects can be reduced, but overhead and energy consumption increase
Solution Approach 1:
The system performs preliminary determination of the access sequence for memory tiles before actual access operations. By pre-planning the access pattern and identifying which tiles need to be accessed and in what order, the system minimizes unnecessary transitions and reduces energy consumption while still managing disturb effects effectively.
Solution Approach 2:
The patent enables consecutive selections and accesses within a single memory tile without requiring transitions to other tiles. This continuity of access operations within the same tile eliminates the overhead and energy consumption associated with tile transitions, while the nonadjacent access pattern manages disturb effects.
3Loss of energy
If consecutive selections are made within a single memory tile, then transitions between tiles are minimized, but disturb effects may impact access efficiency
Solution Approach 1:
Instead of accessing memory locations in sequential or adjacent order, the patent employs a nonadjacent access pattern where memory locations are selected in a specific sequence that skips certain intermediate locations. This inversion of the conventional access pattern allows consecutive selections within a tile while avoiding disturb effects that would otherwise impact access efficiency.
4Ease of operation
If memory locations are selected in conventional patterns, then access operations are simple, but latency increases due to tile transitions
Solution Approach 1:
The system dynamically determines access sequences for memory locations within tiles, optimizing the access pattern to minimize latency. By adaptively selecting which locations to access and in what order, the system reduces the time required for memory operations while maintaining operational simplicity through automated sequence determination.
Data Source
AI summary
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.