Memory Tile Array Architecture for Lower SoC Bandwidth Demand

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Solution Overview

Problem

The increasing data processing capabilities of DPE tiles in integrated circuits lead to higher bandwidth requirements for the SoC interface, necessitating a solution to reduce external memory access and bandwidth demands.

Innovation Solution

Incorporating memory tiles within the DPE array, which are configurable to form composite memories, allowing DPE tiles to access a larger pool of memory and reduce reliance on external memory access through direct memory access engines and stream switches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If DPE tiles increase data processing capabilities, then processing power is improved, but bandwidth requirements on the SoC interface increase

Engineering Contradiction:

Improvedata processing capabilitiesVSAvoidbandwidth requirements

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent combines memory tiles directly within the DPE array architecture, merging previously separate memory resources into the processing fabric. This integration allows DPE tiles to access memory through the stream switch network without requiring external memory interfaces, thereby reducing SoC interface bandwidth requirements while maintaining enhanced processing capabilities.

Inventive Principle:

Principle #5Merging (Combining)

2Quantity of substance

If external memory access is reduced, then bandwidth requirements are lowered, but memory accessibility may be limited

Engineering Contradiction:

Improvebandwidth requirementsVSAvoidmemory accessibility

Core Design Contradiction:

Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The stream switch network is designed to provide universal access to all memory tiles from any DPE tile. The configurable interconnect fabric allows dynamic routing and multiple access patterns, enabling any processing element to access any memory resource within the array, thus maintaining high adaptability and versatility without requiring external memory interfaces.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Quantity of substance

If memory tiles are integrated within the DPE array, then bandwidth requirements on the SoC interface are reduced, but device complexity increases

Engineering Contradiction:

Improvebandwidth requirementsVSAvoidinternal architecture complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The memory system is segmented into multiple independent memory tiles that can be individually configured and accessed. Each memory tile operates as a discrete unit within the larger array, allowing modular integration that manages complexity through systematic decomposition of the memory subsystem into manageable, reusable building blocks.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11336287B1Data processing engine array architecture with memory tiles

Publication Date: 2022.05.17 XILINX INC

AI summary

An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.