Memory Tile Array with Predictable Read Latency
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Solution Overview
Problem
Memory technologies with long write latencies result in unpredictable read latencies due to the time required for write operations, which can cause tail latency when read operations follow write operations, especially in non-volatile memory technologies like NAND flash, FeRAM, MRAM, PCM, and RRAM.
Innovation Solution
A memory system with control logic that allows simultaneous writing to multiple tiles and reading from an entire row, while generating parity bits for error correction and wear leveling, enabling efficient cache line operations and reducing wear on memory cells by rotating parity locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write operations are performed on non-volatile memory cells, then data is stored reliably, but read latency becomes unpredictable and increases due to long write completion times
Solution Approach 1:
The memory system divides the memory array into multiple independent tiles organized in rows and columns. Each tile can be independently accessed for read or write operations. This segmentation allows the system to perform read operations on tiles that are not currently being written to, thereby achieving predictable read latency even when other tiles are undergoing write operations.
Solution Approach 2:
The patent introduces a two-dimensional tile organization (N rows × M columns) with independent row and column decoders. This dimensional structure enables simultaneous read and write operations by selecting different rows or columns, effectively adding spatial dimensionality to operation scheduling and eliminating the sequential dependency between reads and writes.
2Stability of the object's composition
If read operations wait for write operations to complete, then data consistency is maintained, but tail latency increases significantly
Solution Approach 1:
The system performs preliminary actions by pre-positioning data in appropriate tiles and using independent row/column decoders to prepare read paths before write operations complete. The control logic can initiate read operations on independent tiles without waiting for write completion, maintaining data consistency through the architectural design rather than sequential waiting.
Solution Approach 2:
The control logic acts as an intermediary that manages the complexity of simultaneous read and write operations. It tracks which tiles are being written to and routes read operations to independent tiles, mediating between the need for data consistency and the desire for low latency by making intelligent routing decisions.
3Productivity
If multiple cache lines are written simultaneously to different tiles, then write throughput increases, but system complexity increases due to coordination requirements
Solution Approach 1:
The memory array is segmented into N rows and M columns of independent tiles, each with its own decode logic. This segmentation allows the control logic to issue write commands to multiple tiles simultaneously by simply selecting different row-column intersections, achieving high write throughput without complex coordination because each tile operates independently.
Solution Approach 2:
The tile structure serves multiple functions: it can be independently read from, written to, or have parity generated for it. Each tile is a universal unit that can participate in various operations, simplifying control logic because the same basic structure handles all operations uniformly without requiring specialized coordination mechanisms.
4Reliability
If parity bits are generated for error correction, then data reliability improves, but write operations take longer due to additional processing
Solution Approach 1:
Parity bits are generated as a preliminary action during the write operation to the same tile. The control logic generates parity for a tile as it writes data to that tile, rather than as a separate subsequent step. This preliminary generation of parity within the same operation window does not extend the overall write completion time while still providing error correction capability.
Data Source
AI summary
Systems and methods related to a memory system with a predictable read latency from media with a long write latency are described. An example memory system includes an array of tiles configured to store data corresponding to a cache line associated with a host. The memory system further includes control logic configured to, in response to a write command from a host, initiate writing of a first cache line to a first tile in a first row of the tiles, a second cache line to a second tile in a second row of the tiles, a third cache line to a third tile in a third row of the tiles, and a fourth cache line in a fourth row of the tiles. The control logic is configured to, in response to a read command from the host, initiate reading of data stored in an entire row of tiles.