Memory Tile Decoding Architecture for High Density
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Solution Overview
Problem
Current memory devices face challenges in reducing the footprint of decoding circuitry, which limits the density of memory cells that can be packed within a given device area and hampers parallel access operations, leading to suboptimal access speed and data throughput.
Innovation Solution
The proposed decoding architecture for memory tiles involves vertically stacked word line plates with shared electrode structures and pillar tiles that utilize complementary decoders, allowing for reduced decoding circuitry footprint by enabling concurrent access to multiple memory cells and reducing the number of decoders per pillar tile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional decoding architecture is used, then decoding circuitry can be implemented, but the footprint of decoding circuitry is large which limits memory cell density
Solution Approach 1:
Multiple word line plates are vertically stacked and share common electrode structures, combining the decoding functions for multiple word lines into a single decoder unit. This merging reduces the total footprint of decoding circuitry while enabling access to multiple memory cell rows simultaneously, thereby increasing memory cell density.
Solution Approach 2:
The patent transitions from a planar arrangement of word lines to a vertical stacking arrangement. By organizing word line plates in the vertical dimension rather than expanding horizontally, the decoding circuitry footprint is reduced while maintaining the ability to address multiple memory cells, thus increasing density without proportionally increasing the decoder area.
2Speed
If more decoders are added to increase access speed, then parallel access capability improves, but the decoding circuitry footprint increases
Solution Approach 1:
Multiple word line plates share common electrode structures and decoding circuits. A single decoder can control multiple word lines through the shared electrodes, enabling parallel access to multiple memory cell rows without requiring separate decoders for each word line. This maintains high access speed while minimizing the total decoder footprint.
Solution Approach 2:
The electrode structures serve multiple functions: they act as word line selection lines, bit line connections, and decoding control lines simultaneously. This multi-functionality allows a single decoder to perform multiple decoding operations in parallel, improving access speed without proportionally increasing the decoder area.
3Quantity of substance
If decoding circuitry area is reduced, then memory device density increases, but support circuitry integration becomes more challenging
Solution Approach 1:
The decoding circuitry and support circuitry are nested within the vertical stack of word line plates. The electrodes and decoding structures are integrated into the same vertical footprint, allowing support circuitry to be positioned within or adjacent to the memory array structure rather than requiring separate external integration. This nesting enables high density while maintaining manufacturability.
Solution Approach 2:
By moving support circuitry into the vertical dimension through the stacked word line plate structure, the patent eliminates the need for additional horizontal space. Support circuits can be integrated within the same vertical footprint as the memory cells, facilitating high density without compromising ease of manufacture through excessive area expansion.
Data Source
AI summary
Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.