Nonvolatile Memory Junction Formation via Tilt Ion Implantation
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Solution Overview
Problem
The electrical properties of junction regions in nonvolatile memory devices deteriorate due to trapped electrons, leading to increased threshold voltage distribution and leakage current, and the complex process of forming junction regions requires repeated mask processes, increasing manufacturing costs and time.
Innovation Solution
A method of manufacturing nonvolatile memory devices that involves forming first and second junction regions with different ion implantation processes, where the second ion implantation process is a tilt ion implantation with lower impurity concentration, and using spacers to protect the first junction regions, thereby simplifying the process and improving electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between the source select line SSL and the first word line WL0 is increased to prevent electron trapping, then the electrical properties improve, but the device integration density decreases
Solution Approach 1:
The patent applies different ion implantation conditions to different junction regions. Specifically, the first junction region between the source select line and first word line receives a first ion implantation process, while the second junction region between word lines receives a second ion implantation process with different parameters. This local differentiation allows each junction to be optimized for its specific electrical requirements without increasing overall device area, thereby maintaining integration density while improving reliability.
2Manufacturing precision
If repeated mask processes are used to form different junction regions, then the manufacturing precision improves, but the manufacturing complexity and time increase
Solution Approach 1:
The patent merges multiple ion implantation processes into a single unified process step. By designing the gate line structure and spacing such that a single ion implantation process can simultaneously form multiple different junction regions (first junction region between source select line and first word line, second junction region between word lines), the need for repeated mask processes is eliminated. This reduces manufacturing complexity and time while maintaining the precision required for different junction characteristics through careful process parameter selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the deterioration of electrical properties, reduces capacitance, and simplifies the junction region formation process, enhancing the reliability and reducing manufacturing costs of nonvolatile memory devices.
Implementation Method 1
performing a first ion implantation process to form first junction regions in the semiconductor substrate between the first gate lines, between the first gate line and the second gate line, and between the second gate lines
Implementation Method 2
performing a second ion implantation process to form second junction regions in first junction region of the semiconductor substrate between the first gate lines and between the second gate line and the first gate line
Data Source
AI summary
A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed.