Coordinating Memory Systems via Host Time Information

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Solution Overview

Problem

Current data processing systems face challenges in efficiently and stably processing data across multiple memory systems, particularly in managing operations such as map updates and background operations, which can lead to performance deterioration and reduced efficiency.

Innovation Solution

A data processing system and method that includes a first and second memory system, where the first system performs map updates by rearranging Logical Block Address (LBA) information, and the second system selects and prioritizes background operations like garbage collection, wear leveling, and map flush based on workloads and priority, optimizing operations according to time information received from a host.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the first memory system performs map updates by successively rearranging LBA information, then the data processing speed is improved, but the system stability deteriorates due to continuous update operations

Engineering Contradiction:
Improvedata processing speedVSAvoidsystem stability
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

The host generates time information in advance based on the number of commands and data size before transmitting operation commands to the memory systems. This preliminary calculation of processing time allows the memory systems to perform map updates and background operations within predetermined time windows, preventing continuous updates that would cause instability while maintaining processing speed.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the second memory system performs multiple background operations simultaneously, then the workload processing capacity is improved, but the operation reliability deteriorates due to resource contention

Engineering Contradiction:
Improveworkload processing capacityVSAvoidoperation reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The second memory system divides background operations into different priority levels and executes them sequentially based on priority rather than simultaneously. High-priority operations are completed first, followed by lower-priority operations, ensuring that resource contention is minimized while still processing multiple workloads efficiently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory system dynamically adjusts the execution order and timing of background operations based on current workload conditions and priority levels. The system can pause or resume operations as needed, optimizing resource utilization while maintaining operational reliability under varying load conditions.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If the host transmits operation commands to multiple memory systems without time information, then the system complexity is reduced, but the data processing efficiency deteriorates due to uncoordinated operations

Engineering Contradiction:
Improvesystem complexityVSAvoiddata processing efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The host generates and transmits time information as an additional parameter with operation commands to multiple memory systems. This time information parameter enables coordinated processing across memory systems without requiring complex control logic, as each system independently uses the provided time window to perform its operations in sync with others.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10055131B2Data processing system of efficiently processing data in a plurality of memory systems and operating method of controlling data processing system
Publication Date: 2018.08.21 SK HYNIX INC
  • US10055131B2 patent drawing
  • US10055131B2 patent drawing
  • US10055131B2 patent drawing

AI summary

A data processing system may include: a first memory system including a first memory device, and a first controller of the first memory device; and a second memory system including a second memory device, and a second controller of the second memory device, the first memory system may receive a command from a host, and then checks time information included in the command and performs a first update operation for the first memory device for a first time corresponding to the time information, and the second memory system may perform a second update operation for the second memory device for the first time for which the first update operation is performed.