Memory-Based Timing Channel Circuitry for Implantable Stimulators
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Solution Overview
Problem
The existing timing channel circuitry in implantable stimulator devices lacks flexibility in generating complex pulses, such as ramped currents, due to limitations in register bank design, which restricts the production of more intricate pulse shapes and increases layout and power consumption.
Innovation Solution
The implementation of a memory-based timing channel circuitry that stores pulse parameters, using a dual-port memory addressable by an address bus, allows for a variable number of words per phase, reducing the need for extensive registers and enabling the creation of more complex pulses without increasing layout area or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a memory-based timing channel circuitry is implemented to store pulse parameters, then flexibility in generating complex pulses is improved, but device complexity increases
Solution Approach 1:
The dual-port memory structure serves multiple functions: it stores pulse parameters, generates timing signals, and provides data to multiple timing channels simultaneously. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby improving flexibility while managing device complexity.
Solution Approach 2:
The system enables dynamic changes in pulse parameters (amplitude, width, shape) by storing multiple parameter sets in memory and selectively retrieving them. This allows complex pulse generation through parameter variation rather than requiring complex hardware circuitry, resolving the contradiction between flexibility and device complexity.
2Adaptability or versatility
If extensive registers are used to store pulse parameters for each phase, then pulse generation flexibility is improved, but layout area increases
Solution Approach 1:
Multiple timing channels share a common dual-port memory structure rather than each channel having separate registers. This merging of storage resources allows flexible pulse generation for multiple channels while significantly reducing the total layout area compared to dedicated registers for each channel.
Solution Approach 2:
The patent transitions from a time-multiplexed approach (using separate registers for each phase) to a spatial approach (using a dual-port memory that can be addressed simultaneously). This dimensional change in data organization allows efficient storage of complex pulse parameters without proportionally increasing layout area.
3Adaptability or versatility
If extensive registers are used to store pulse parameters, then pulse generation flexibility is improved, but power consumption increases
Solution Approach 1:
Multiple timing channels share a common dual-port memory structure rather than each channel having separate registers. This merging of storage resources allows flexible pulse generation for multiple channels while significantly reducing the total layout area compared to dedicated registers for each channel.
Solution Approach 2:
The dual-port memory structure serves multiple functions: it stores pulse parameters, generates timing signals, and provides data to multiple timing channels simultaneously. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby improving flexibility while managing device complexity.
4Productivity
If a dual-port memory is used to store pulse parameters, then handling of multiple timing channels is improved, but device complexity increases
Solution Approach 1:
The dual-port memory structure serves multiple functions: it stores pulse parameters, generates timing signals, and provides data to multiple timing channels simultaneously. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby improving flexibility while managing device complexity.
Solution Approach 2:
The timing channel circuitry uses the dual-port memory to automatically manage pulse parameter storage and retrieval without requiring external intervention. The memory's dual-port architecture enables simultaneous read/write operations, allowing multiple timing channels to be handled efficiently with minimal additional control logic.
Data Source
AI summary
Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.