Memory Timing Drift Calibration with a Low-Frequency Clock Copy
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Solution Overview
Problem
Memory systems face timing drift issues due to temperature and voltage variations, causing phase misalignment between memory devices and controllers, which existing technologies fail to address effectively during data transport operations.
Innovation Solution
A memory system that uses a low-frequency slow clock signal to determine phase delays in the memory device, allowing for accurate calibration and synchronization of high-frequency clock signals by mimicking the clock distribution characteristics, enabling phase adjustments for optimal data transport.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-frequency clock signals are used for data transport, then data transport efficiency is improved, but timing drift due to temperature and voltage variations causes phase misalignment between memory devices and controllers
Solution Approach 1:
The patent uses a low-frequency copy of the high-frequency clock signal to measure timing drift. By creating a simplified version (low-frequency clock) that replicates the distribution path characteristics, the system can accurately measure phase delays without being constrained by power consumption limitations, then apply these measurements to compensate for drift in the actual high-frequency data transport operations
Solution Approach 2:
The low-frequency clock signal serves as an intermediary that enables indirect measurement of timing drift. Instead of directly measuring drift in the high-frequency clock (which would require continuous power), the system uses the low-frequency clock as a mediator to probe the same distribution path, obtain drift measurements, and transfer this information back to adjust the high-frequency clock synchronization
2Reliability
If continuous clock signal monitoring is performed to detect timing drift, then timing synchronization is improved, but power consumption increases preventing power-saving modes
Solution Approach 1:
The system performs drift measurement using the low-frequency clock signal periodically rather than continuously. The low-frequency nature of this measurement clock allows the system to enter power-saving modes between measurement cycles, as the reduced frequency inherently lowers power consumption during monitoring while still providing periodic updates to maintain synchronization accuracy
Solution Approach 2:
The patent changes the frequency parameter of the measurement clock from high-frequency to low-frequency. This parameter change fundamentally alters the power consumption characteristics, enabling the monitoring function to operate during power-saving modes. The low-frequency clock maintains sufficient resolution for drift detection while consuming minimal power, allowing the memory controller to transition between active and power-saving states
Data Source
AI summary
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.