Stacked Semiconductor Memory Timing Control via Core Chip Inversion
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Solution Overview
Problem
In semiconductor memory devices with separate front-end and back-end units, operation speed deviations among core chips due to manufacturing process conditions lead to reduced latch margin and potential inaccuracies in read data latching, necessitating multiple latch timing control circuits on the interface chip, resulting in inefficient chip structure and waste.
Innovation Solution
Each core chip is equipped with an output timing adjustment circuit to synchronize the time required to receive and output read data, eliminating the need for multiple latch timing control circuits on the interface chip by ensuring uniform operation timing across all core chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple latch timing control circuits are provided on the interface chip to accommodate operation speed differences among core chips, then read data accuracy is improved, but chip structure complexity and resource waste increase
Solution Approach 1:
Instead of having the interface chip control the timing of each core chip through multiple latch timing control circuits, the invention inverts the control direction by equipping each core chip with its own output timing adjustment circuit. This allows each core chip to independently adjust its output timing based on its operation speed, eliminating the need for multiple control circuits on the interface chip while ensuring synchronized data output.
Solution Approach 2:
The timing control function is segmented from the interface chip and distributed to individual core chips. Each core chip now has its own output timing adjustment circuit that operates independently, allowing for localized timing adjustments without affecting other core chips or requiring complex centralized control.
2Manufacturing precision
If each core chip operates independently with its own timing adjustments, then operation speed variations are compensated, but the number of control circuits on the interface chip increases
Solution Approach 1:
The control architecture is inverted from centralized timing control on the interface chip to distributed timing adjustment on each core chip. This eliminates the need for multiple latch timing control circuits on the interface chip while maintaining operation speed consistency through independent adjustments at the source.
3Device complexity
If the interface chip uses a common latch timing control for all core chips, then chip structure is simplified, but read data accuracy decreases due to operation speed differences
Solution Approach 1:
The timing control function is segmented and distributed to individual core chips through output timing adjustment circuits. Each core chip independently adjusts its output timing based on its operation speed, eliminating the need for complex centralized control while ensuring accurate read data synchronization.
4Reliability
If latch timing control circuits are provided for all possible core chips, then timing accuracy is improved, but chip area is wasted when fewer core chips are used
Solution Approach 1:
The timing control functionality is segmented and embedded in each core chip rather than providing all possible control circuits on the interface chip. This allows the system to use only the timing adjustment circuits corresponding to the actual number of core chips connected, eliminating area waste while maintaining latch timing accuracy.
Data Source
AI summary
A semiconductor device includes an interface chip including: an internal data terminal, and a timing data storage circuit configured to output a plurality of timing set signals, and a plurality of core chips stacked with one another, each of the core chips including a plurality of memory cells, an output control circuit coupled to the timing data storage circuit of the interface chip, the output control circuit being configured to receive a corresponding one of the timing set signals and to output an output timing signal in response to the corresponding one of the timing set signals, and a data output circuit coupled to the internal data terminal of the interface chip, the data output circuit being configured to output data in response to the output timing signal, the data being derived from a corresponding one of the memory cells.