Memory Timing Drift Detection Using Low-Frequency Phase Measurement
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Solution Overview
Problem
Memory systems face timing drift issues due to temperature and voltage variations, causing phase misalignment between the memory device and controller timing references, which existing technologies fail to accurately and efficiently address.
Innovation Solution
A memory system that uses a low-frequency slow clock signal to determine phase delays in the memory device, allowing for phase adjustments in the memory controller, thereby maintaining synchronization during data transport, and includes a drift detection circuit with configurable replica delay elements and phase to digital converters to accurately measure and correct timing drift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a timing reference is used in memory device and controller, then data transport can be synchronized, but timing drift occurs due to temperature and voltage variations causing phase misalignment
Solution Approach 1:
The patent applies preliminary action by performing drift detection and phase calibration before actual data transport operations. The memory device measures phase drift of the timing reference signal and communicates drift information to the controller in advance, allowing the controller to pre-adjust its timing reference phase. This ensures synchronization accuracy is maintained during subsequent data transport without real-time instability.
2Productivity
If high-frequency timing signals are used for data transport, then data transport speed is improved, but timing drift measurement becomes more difficult and power consumption increases
Solution Approach 1:
The patent introduces an intermediary approach by using a low-frequency test signal as a mediator to measure timing drift. Instead of directly measuring drift in the high-frequency data transport timing signal, the system uses a separate low-frequency test signal that passes through the same timing reference distribution path. This intermediary signal is easier to measure with higher precision, and its measured drift is then applied to correct the high-frequency timing reference, achieving accurate drift compensation without the difficulties of direct high-frequency measurement.
Solution Approach 2:
The patent applies parameter changes by transitioning from measuring high-frequency timing signal drift to measuring low-frequency test signal drift. The frequency parameter of the test signal is deliberately changed to a lower value that is more suitable for accurate phase measurement. This parameter change enables precise drift detection while maintaining the high-frequency data transport performance, as the corrected timing reference is then applied to the high-frequency operational signals.
3Measurement precision
If complex calibration processes are implemented to correct timing drift, then synchronization accuracy is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the drift detection function into a separate, dedicated drift detection circuit within the memory device. This extracted module specifically measures phase drift of the timing reference signal using a low-frequency test signal and communicates the drift information to the controller. By separating this measurement function from the main data transport path and using a simplified low-frequency measurement approach, the overall system complexity is reduced while maintaining high measurement precision. The controller then applies the extracted drift information to adjust its timing reference without requiring complex calibration circuits.
Data Source
AI summary
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.