Dual-Controller Memory Timing Synchronization Across Four Lanes
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Solution Overview
Problem
Non-volatile memory devices face challenges with slower read/write speeds and timing skew issues that degrade performance, particularly in systems adhering to the UFS standard, which affect bandwidth and data processing efficiency.
Innovation Solution
A memory device design incorporating two memory controllers connected by a signal line, exchanging timing information and correcting signal timing across four lanes to minimize timing skew, with temperature-based performance limiting mechanisms to maintain optimal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory devices are used to provide high capacity and low power consumption, then storage reliability and energy efficiency are improved, but read/write speeds deteriorate compared to volatile memory devices
Solution Approach 1:
The memory device is divided into multiple independent memory controllers (first memory controller and second memory controller) that operate in parallel. Each controller manages specific memory banks and communicates through dedicated signal lines, enabling simultaneous data operations that collectively improve throughput while maintaining non-volatile storage reliability
Solution Approach 2:
The patent introduces a new communication dimension between memory controllers by establishing direct signal line connections (first signal line and second signal line) that enable timing information exchange. This additional communication pathway allows synchronized parallel operations across multiple controllers, effectively increasing data processing bandwidth without compromising storage reliability
2Productivity
If multiple memory controllers are connected through signal lines to increase bandwidth, then data processing capacity is improved, but timing skew between signals deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where timing information is continuously exchanged between memory controllers through dedicated signal lines. The first memory controller transmits timing information to the second memory controller via the first signal line, and the second controller responds through the second signal line, enabling real-time synchronization that compensates for timing skew and maintains signal integrity across parallel channels
Solution Approach 2:
Dedicated signal lines act as intermediaries between memory controllers, carrying timing information that mediates synchronization. These signal lines serve as communication channels that translate and coordinate timing signals across different controller domains, ensuring that parallel operations remain synchronized despite physical separation and potential timing variations
3Productivity
If memory controllers operate at high performance to increase data processing speed, then bandwidth is improved, but temperature increase deteriorates system stability
Solution Approach 1:
The system divides data processing workload across multiple independent memory controllers that operate in parallel. By segmenting the processing load, each controller handles a portion of the total data throughput, reducing individual controller thermal generation while collectively achieving high bandwidth through coordinated parallel operations
Data Source
AI summary
A memory device includes a first non-volatile memory, a second non-volatile memory, a first memory controller including a first interface, and the first memory controller configured to control an operation of the first non-volatile memory, and a second memory controller including a second interface, and the second memory controller configured to control an operation of the second non-volatile memory. The first memory controller and the second memory controller are connected by at least one signal line, the first memory controller and the second memory controller are configured to exchange timing information of a plurality of signals transmitted through first to fourth lanes through the signal line, and the first memory controller and the second memory controller are configured to correct a timing of the each of the plurality of signals transmitted through the first to fourth lanes, based on the timing information.