Memory AC Timing Measurement Circuit Architecture
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Solution Overview
Problem
Current automatic testing machines (ATE) are not suitable for accurately measuring AC timing parameters of memory due to low resolution, signal errors during transmission, difficulty in determining true timing measurements, and a large number of pins required for input and output, which affects measurement accuracy and efficiency.
Innovation Solution
A memory timing measurement circuit and architecture that includes a clock tree to generate balanced test signals, timing measurement units (TMUs) with delay circuits and multiplexers to adjust signal timing, and a testing method that reduces off-chip signal variations by generating test signals internally and measuring AC timing parameters with high precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If ATE is used for timing measurement, then automation is achieved, but measurement precision deteriorates due to low resolution (350 ps vs. several decades of ps)
Solution Approach 1:
The patent introduces an intermediary timing measurement circuit between the ATE and the memory under test. This intermediary circuit includes a delay circuit with adjustable delay and a ring oscillator that generates high-frequency test signals internally. The intermediary circuit converts the low-resolution ATE measurements into high-precision internal measurements by using its own high-frequency oscillations as a reference, thereby resolving the contradiction between automation and measurement precision.
Solution Approach 2:
The patent replaces the mechanical/electrical signal transmission system of the ATE with an internal electronic timing measurement system. Instead of relying on external signal transmission through routing and signal lines, the system uses internal ring oscillators and delay circuits to generate and measure timing parameters directly within the memory chip, eliminating the source of measurement errors.
2Ease of operation
If ATE sends test signals through circuit board routings, then testing is enabled, but signal errors increase due to routing and signal line variations
Solution Approach 1:
The patent extracts the timing measurement function from the external ATE system and relocates it inside the memory chip. By taking out the timing measurement circuitry and placing it within the chip itself, the system eliminates the routing and signal line variations that cause errors during external signal transmission, thereby improving reliability while maintaining testing capability.
Solution Approach 2:
The memory chip performs self-testing by using its internal timing measurement circuit to measure its own timing parameters. The ring oscillator generates test signals internally, and the delay circuit compares these internal signals against the actual memory operation timing, allowing the chip to self-diagnose and self-measure without external intervention, thus eliminating external signal transmission errors.
3Measurement precision
If timing measurement is performed externally, then measurement is enabled, but true timing value remains unknown due to signal transmission errors
Solution Approach 1:
The patent implements a feedback mechanism where the timing measurement circuit continuously monitors and compares internal timing signals against the actual memory operation timing. The ring oscillator generates reference signals that are fed back through the delay circuit to the timing measurement unit, which then compares these feedback signals with the actual data input/output timing to determine accurate timing parameters, eliminating the loss of true timing information.
4Ease of operation
If multiple external pins are used for test signals, control signals, and clock signals, then testing is enabled, but chip area increases due to large number of pins
Solution Approach 1:
The patent makes the timing measurement circuit universal by integrating multiple functions into a single circuit block. The same circuit that generates timing signals also performs measurement, comparison, and data processing functions. This multi-functionality eliminates the need for separate dedicated pins for each function, thereby reducing the total number of pins required while maintaining full testing capability.
Data Source
AI summary
A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured.