Memory Timing Overlap Circuit for Activate Precharge Operations

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Solution Overview

Problem

Memory devices, such as MRAM, face limitations in clock cycles for precharge and activate operations due to external timing constraints, which can lead to errors and reduced compatibility with various systems.

Innovation Solution

Incorporating an overlap circuit, like an AND gate, that allows the memory device to receive and execute activate commands before completing precharge operations, utilizing combined clock cycles from tRP and tRCD to perform both operations, thereby increasing flexibility and compatibility with external sources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the memory device waits for precharge operations to complete before receiving activate commands, then operation reliability is improved, but timing flexibility and compatibility with external sources deteriorate

Engineering Contradiction:

Improveoperation reliabilityVSAvoidtiming flexibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The memory device performs precharge operations in advance before the activate command is received, so that when the activate command arrives, the precharge is already complete or nearly complete, eliminating the need to wait and enabling timely response to external commands while maintaining operational reliability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The memory device dynamically adjusts its operation timing based on when commands are received from external sources, allowing flexible overlap of precharge and activate operations rather than rigid sequential execution, thus adapting to varying external timing requirements while ensuring operations complete reliably

Inventive Principle:

Principle #15Dynamics

2Manufacturing precision

If the memory device uses separate clock cycles for precharge and activate operations, then operation precision is improved, but productivity and time utilization deteriorate

Engineering Contradiction:

Improveoperation precisionVSAvoidtime utilization

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The memory device merges the timing of precharge and activate operations by allowing them to overlap in time, utilizing the same clock cycle infrastructure for both operations rather than dedicating separate exclusive time slots, thus improving time utilization while maintaining precise control over each operation's completion

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The memory device ensures continuous operation by initiating activate commands immediately when received, while precharge operations continue in the background without interruption, maximizing the utilization of clock cycles and eliminating idle time between operations

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS9870812B2Memory system with timing overlap mode for activate and precharge operations

Publication Date: 2018.01.16 EVERSPIN TECHNOLOGIES INC

AI summary

In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.