Semiconductor Memory Top Electrode Boron Doping Strategy
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Solution Overview
Problem
The integration of semiconductor memory devices is hindered by the need for new and expensive exposure techniques to achieve finer patterns, leading to process defects and reduced yield due to challenges in burying word lines inside semiconductor substrates.
Innovation Solution
A semiconductor memory device is fabricated with a top electrode comprising a first metal layer, a silicon-germanium layer, a second metal layer, and a silicon layer, where the silicon-germanium layer has a higher boron content than the silicon layer, and a dielectric layer covering bottom electrodes, which helps in preventing warpage and improving refresh characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If new exposure techniques are used to achieve finer patterns, then manufacturing precision is improved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent changes the material composition parameters of the top electrode by introducing a silicon-germanium layer with specific boron concentration (1×10^19 to 1×10^21 atoms/cm³), which enables pattern formation without requiring advanced exposure techniques, thus achieving fine patterns while avoiding increased device complexity
Solution Approach 2:
The patent uses a composite top electrode structure comprising multiple layers including a silicon-germanium layer combined with metal layers (e.g., platinum, iridium, or钌). This composite structure provides both the electrical functionality and the mechanical properties needed for reliable capacitor electrodes without requiring complex exposure processes
2Productivity
If word lines are buried inside semiconductor substrates, then integration density is improved, but process defects increase due to fabrication challenges
Solution Approach 1:
The patent segments the electrode structure into distinct bottom electrode and top electrode components separated by a dielectric layer, with the top electrode formed through a simplified planar process. This segmentation allows the word lines to be buried in the substrate while the capacitor electrodes are formed separately above, reducing process defects associated with burying conductors
Solution Approach 2:
The patent transitions from planar electrode formation to a vertical stack structure where the top electrode is formed above the dielectric layer that covers the bottom electrode. This dimensional change allows integration density improvement through vertical stacking rather than through complex buried word line formation
3Reliability
If boron content is increased in the silicon layer, then electrical conductivity is improved, but air defects increase
Solution Approach 1:
The patent applies local quality by concentrating boron doping in the silicon-germanium layer rather than the silicon layer. The silicon-germanium layer has high boron concentration for electrical conductivity, while the silicon layer has low or zero boron content to avoid air defects, thus achieving both conductivity and reliability
Solution Approach 2:
The silicon-germanium layer acts as an intermediary between the metal layers and the silicon layer, providing the necessary electrical conductivity through boron doping while protecting the silicon layer from excessive boron content that would cause air defects. The germanium component also provides mechanical stress control
4Ease of manufacture
If a simple top electrode structure is used, then fabrication cost is reduced, but refresh characteristics deteriorate
Solution Approach 1:
The patent uses composite materials in the top electrode structure, combining metal layers (platinum, iridium, or钌) with a silicon-germanium layer. This composite structure provides both ease of fabrication through standard deposition processes and improved refresh characteristics through the electrical and mechanical properties of the silicon-germanium layer
Solution Approach 2:
The patent optimizes parameter changes by controlling the thickness of each layer (metal layers: 5-50 nm, silicon-germanium layer: 5-50 nm) and the boron concentration (1×10^19 to 1×10^21 atoms/cm³) to achieve good refresh characteristics while maintaining fabrication simplicity and cost-effectiveness
Data Source
AI summary
Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a semiconductor substrate that includes a cell array region and a peripheral region, a plurality of bottom electrodes on the semiconductor substrate on the cell array region, a dielectric layer that conformally covers sidewalls and top surfaces of the bottom electrodes, and a top electrode on the dielectric layer and between the bottom electrodes. The top electrode includes a first metal layer, a silicon-germanium layer, a second metal layer, and a silicon layer that are sequentially stacked. An amount of boron in the silicon-germanium layer is greater than an amount of boron in the silicon layer.