Memory Cell Touch-Up Programming With Analog Bitline Voltage
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Solution Overview
Problem
Existing memory sub-systems face inefficiencies in programming time and power consumption due to the need for extensive program verify operations during touch-up programming, particularly in high threshold voltage distributions.
Innovation Solution
Implementing a level-by-level touch-up programming method that reduces the number of program and verify pulses by applying incremental program pulses and analog bitline voltages to adjust cell voltages, allowing for faster and more efficient programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If extensive program verify operations are performed during touch-up programming, then programming precision is improved, but programming time increases
Solution Approach 1:
The patent segments the programming process into multiple levels (first level and second level programming operations). The first level performs initial programming with verify operations, and the second level performs touch-up programming with reduced verify operations. This segmentation allows the system to achieve programming precision through multiple passes while reducing overall time by avoiding redundant verify operations in subsequent passes.
Solution Approach 2:
The patent applies partial action by performing verify operations selectively rather than exhaustively. In the second level programming operation, the system performs verify operations only for cells that require touch-up programming, rather than verifying all cells. This partial verification approach maintains sufficient programming precision while significantly reducing the time and energy consumed by extensive verify operations.
2Manufacturing precision
If extensive program verify operations are performed during touch-up programming, then programming precision is improved, but power consumption increases
Solution Approach 1:
The patent divides the programming operation into two levels, with the second level focusing only on cells requiring touch-up programming. By segmenting the verify operations to apply only where necessary, the system maintains programming precision for affected cells while reducing overall power consumption compared to performing complete verify operations on all cells.
Solution Approach 2:
The system performs verify operations partially, only for cells identified as needing touch-up programming in the second level operation. This selective verification approach ensures programming precision is maintained for the necessary cells while avoiding the excessive power consumption that would result from verifying all cells in the memory array.
3Reliability
If traditional touch-up programming is used, then programming completeness is ensured, but device complexity increases
Solution Approach 1:
The patent segments the programming control into two distinct levels: first level programming for initial cell programming, and second level programming for touch-up operations. This segmentation simplifies the control logic by handling different programming scenarios separately, making the overall system more manageable while ensuring programming completeness through the coordinated operation of both levels.
Solution Approach 2:
The second level programming operation applies partial verify operations only to cells requiring touch-up programming, rather than implementing a comprehensive verify operation for all cells. This partial action approach reduces the complexity of the control system by avoiding unnecessary verification steps while still ensuring programming completeness for the affected cells.
Data Source
AI summary
Control logic in a memory device causes a primary program operation to be initiated on the memory array. The primary program operation includes multiple primary program pulses and corresponding verify pulses. The control logic causes a secondary program operation to be initiated on the memory array. The secondary program operation includes causing multiple sensing pulses to be applied to the memory array to determine a plurality of measured threshold voltages corresponding to the memory array, determining bitline voltages based on the multiple measured threshold voltages, causing the bitline voltages to be applied to at least one set of cells of the plurality of memory cells, and causing multiple secondary program pulses to be applied to the at least one set of cells.


