Memory Tracking Circuit for Read Margin and Access Time
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory circuits face reading errors due to insufficient read margin caused by weak driving ability of memory cell arrays and inadequate delay in sense amplifier enable signals, especially when voltage levels change, leading to inaccurate data detection and increased access time.
Innovation Solution
A memory circuit with a tracking circuit that includes dummy cells and a dummy bit line, which delays the word-line pulse signal to generate a sense amplifier enable signal, allowing for extended discharge time of the bit line and improving data bit detection accuracy by compensating for transistor threshold voltage mismatches and varying voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay time between word line enable and sense amplifier enable is extended to increase read margin, then data detection accuracy is improved, but access time is increased
Solution Approach 1:
The tracking circuit dynamically adjusts the delay time based on voltage levels. When voltage levels change, the tracking circuit modifies the delay period accordingly, allowing the system to optimize between read margin and access time under different operating conditions rather than using a fixed delay
Solution Approach 2:
The invention changes the delay parameter adaptively by using dummy cells with different transistor threshold voltages to create variable delay periods. This allows the system to adjust the delay time parameter to match different voltage supply levels, resolving the contradiction between needing sufficient delay for accurate detection and minimizing access time
2Use of energy by moving object
If voltage supply level is lowered to reduce power consumption, then energy usage is reduced, but read margin decreases leading to reading errors
Solution Approach 1:
The tracking circuit acts as a feedback mechanism that monitors voltage levels and automatically adjusts the delay period to compensate for changes in read margin. When voltage is lowered to save power, the tracking circuit extends the delay to maintain sufficient read margin, and when voltage is increased, it reduces delay to maintain optimal access time
Solution Approach 2:
The dummy cells perform preliminary action by pre-charging or pre-discharging the dummy bit line to counteract the effects of voltage changes before the actual sensing operation begins, ensuring that the sense amplifier receives properly conditioned signals regardless of supply voltage level
3Measurement precision
If dummy cells with high threshold voltage transistors are used to extend delay period, then read margin is improved at low voltage, but delay mismatch occurs with standard threshold voltage transistors
Solution Approach 1:
The invention applies local quality by using different transistor threshold voltages in specific locations within the tracking circuit. High threshold voltage transistors are used in dummy cells where extended delay is needed, while standard threshold voltage transistors are used in other parts where matching speed is critical, creating locally optimized performance
Data Source
AI summary
A tracking circuit of a memory circuit is provided. The tracking circuit is coupled between a control circuit and a sense amplifier, delays a word-line pulse signal generated by the control circuit by a delay period to generate a sense amplifier enable signal enabling the sense amplifier to detect data bits output by a memory cell array. In one embodiment, the tracking circuit comprises a plurality of dummy cells and a dummy bit line. At least one of the plurality of dummy cells comprises a plurality of cascaded transistors cascaded between the dummy bit line and a ground voltage for lowering down a dummy bit line signal on the dummy bit line when the word-line pulse signal is enabled. The dummy bit line is coupled to the dummy cells and carries the dummy bit line signal.