Memory Tracking Circuit for Read Access Time Reduction
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Solution Overview
Problem
Conventional memory tracking schemes face time delay issues due to incomplete read tracking operations and separate Sense Amplifier Enable signal delays, leading to potential tracking function failures and increased read access times.
Innovation Solution
The proposed tracking scheme tracks time delays along both the column and row of the memory bit cell array, ensuring complete read tracking before new addresses are received, and combines tracking and Sense Amplifier Enable signals to eliminate extra delays, using a configuration where tracking bit cells with similar structures to regular bit cells enable sense amplifiers based on tracking data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional tracking scheme with tracking row and column at the bottom of memory bit cell array is used, then the tracking structure is simple, but the read tracking operation may not complete before input latch clock reset causing tracking function failure
Solution Approach 1:
The patent inverts the conventional tracking approach by placing the tracking row at the top of the memory bit cell array instead of at the bottom, and changes the signal propagation direction. This inversion allows the tracking operation to complete before the input latch clock reset, ensuring reliable tracking function while maintaining structural simplicity.
Solution Approach 2:
The tracking operation is performed in advance before the main read operation. The tracking row is activated beforehand to establish reference timing, and the tracking completion signal is generated before the input latch clock needs to be reset, ensuring that tracking data is ready and reliable before new addresses are processed.
2Reliability
If Sense Amplifier Enable signal is driven from instance center to edge of memory array, then the signal coverage is complete, but extra time delay is introduced in read tracking operation
Solution Approach 1:
The patent changes the signal propagation dimension by activating sense amplifiers through the tracking row in a column-by-column manner from left to right, rather than driving signals from the center to the edge. This dimensional change in signal activation allows complete coverage while reducing the maximum propagation distance and time delay.
Solution Approach 2:
The memory array is segmented into multiple columns, and sense amplifiers are activated sequentially column by column. This segmentation allows the Sense Amplifier Enable signal to propagate shorter distances in each segment, reducing overall time delay while ensuring complete activation of all sense amplifiers across the array.
Data Source
AI summary
A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.