Memory Tracking Circuit with Dummy Bit Line for Timing Compensation
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Solution Overview
Problem
Existing memory circuits face performance degradation due to timing differences caused by process variations and voltage supply variations, which current tracking circuits attempt to compensate for on a worst-case basis, even when the memory is not in RTA mode.
Innovation Solution
A memory circuit with a tracking circuit that includes a dummy bit line, which discharges in response to a signal and a wordline activation signal, enabling timely access to memory cells by generating appropriate enable signals based on peripheral voltage supply variations, thus minimizing performance degradation across different modes of operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tracking circuits operate on a worst-case basis to compensate for timing differences, then reliability is improved, but productivity deteriorates due to performance degradation
Solution Approach 1:
The tracking circuit dynamically adjusts its operation based on the actual mode of operation. In RTA mode, it operates on worst-case basis to ensure timing accuracy, while in non-RTA modes, it reduces its intervention to maintain normal performance. This dynamic adaptation resolves the contradiction by making the compensation mechanism active only when necessary.
Solution Approach 2:
The circuit changes its operational parameters based on the mode of operation. The tracking circuit monitors whether the memory is operating in RTA mode or standard mode, and adjusts its compensation behavior accordingly. This parameter change allows the system to maintain reliability when needed while preserving productivity during normal operation.
2Reliability
If tracking circuits compensate for timing differences in all modes, then reliability is improved, but device complexity increases
Solution Approach 1:
The tracking circuit is segmented into different operational paths or modes. It has a worst-case compensation path that is activated only in RTA mode, and a normal operation path for standard modes. This segmentation allows the complex compensation mechanism to be isolated to only when needed, reducing overall operational complexity.
Solution Approach 2:
The circuit determines the mode of operation in advance and prepares the appropriate tracking behavior. By knowing whether RTA mode is active before executing tracking operations, the circuit can avoid unnecessary complex compensation actions, thereby reducing operational complexity while maintaining reliability when required.
Data Source
AI summary
Memory circuit and a tracking circuit thereof. The tracking circuit includes a dummy bit line (DBL). The tracking circuit further includes a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal. The wordline activation signal causes activation of a memory cell. The tracking circuit also includes a second circuit which is responsive to discharge of the dummy bit line to enable access to the memory cell.