Memory Bit-Line Tracking Circuits for PVT-Stable Margin Delays
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Solution Overview
Problem
Conventional inverter chains used for creating between margin delays in memory devices are unable to consistently account for process, voltage, and temperature variations, leading to inconsistent delays and increased power consumption.
Innovation Solution
Implementing parallel tracking circuits that mimic the electrical characteristics of memory cells to create delays that adjust according to PVT changes, ensuring consistent between margin delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional inverter chains are used for creating between margin delays, then the delay structure is simple, but the delays become inconsistent under PVT variations and power consumption increases
Solution Approach 1:
The patent creates a copy of the actual memory cell circuit (tracking circuit) that replicates its electrical characteristics including capacitance and resistance. This copy is used to generate tracking signals that automatically adapt to PVT variations, providing consistent delay without requiring complex adjustment mechanisms. The tracking circuit copies the essential electrical behavior of the real cell to enable accurate timing reference.
Solution Approach 2:
The tracking circuit receives the same control signals as the actual memory cell and generates output signals that reflect the actual cell's electrical state. This feedback mechanism allows the system to automatically compensate for PVT variations by using the tracking circuit's output as a reference for timing adjustments, ensuring consistent between-margin delays under varying conditions.
2Productivity
If conventional inverter chains are used for delays, then the circuit area is small, but timing tolerances cannot be tightened and throughput is limited
Solution Approach 1:
The tracking circuit dynamically adapts to PVT variations by automatically adjusting its electrical characteristics to match the actual memory cell's state. This dynamic adaptation allows the system to maintain optimal timing margins under varying conditions, enabling tighter timing tolerances and higher throughput without requiring static, over-conservative delay design.
3Adaptability or versatility
If conventional inverter chains are used, then power consumption is high, but delay adjustment for PVT variations is not achieved
Solution Approach 1:
The tracking circuit serves multiple functions: it generates timing reference signals, compensates for PVT variations, and provides electrical characteristic matching all within a single circuit structure. This multi-functionality eliminates the need for separate adjustment circuits and reduces overall power consumption while achieving adaptability to PVT variations.
Data Source
AI summary
Memory devices, circuits, and a method of operating the same are disclosed. In one aspect, a memory system includes a memory array comprising a bit line. The memory system includes a tracking memory cell array coupled to a tracking bit line that mimics an electrical characteristic of the bit line of the memory array. The memory system includes a tracking pre-charge circuit configured to pre-charge the tracking bit line according to a charge time of the bit line to create sufficient between margin for memory operations of the memory array.