Memory Training by Clock Frequency for Faster Power State Startup
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Solution Overview
Problem
The long startup times in computer systems due to slow memory training sequences for multiple power states in DRAMs, particularly in systems with multiple memory channels, ranks, and clock frequencies, result in poor user experience.
Innovation Solution
Implementing a data processing system that selectively trains memory only when the memory clock frequency differs from a previously trained power state, using shadow registers to copy trained parameters for same-frequency power states, thereby reducing training time by replacing repetitive parameter training with a single mode register write command.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory training is performed for each power state with multiple memory clock frequencies, then memory operates reliably at each frequency, but startup time increases significantly
Solution Approach 1:
The patent stores trained parameter sets in shadow registers for each memory clock frequency. When transitioning between power states, if the target frequency has been previously trained, the system copies the trained parameters from shadow registers instead of performing full training again. This copying mechanism maintains memory operation reliability while significantly reducing startup time by avoiding repetitive training for same-frequency power states
Solution Approach 2:
The patent performs memory training in advance for each unique memory clock frequency and stores the trained parameters in shadow registers during system initialization. This preliminary action ensures that when power states are transitioned later, the system can quickly retrieve pre-trained parameters through copying, rather than performing time-consuming training sequences at each power state transition
2Productivity
If memory training parameters are stored for multiple power states, then power state transitions are faster, but device complexity increases
Solution Approach 1:
The shadow registers serve multiple functions: they store trained parameters for different memory clock frequencies, act as a cache for rapid parameter retrieval, and enable quick power state transitions. This multi-functional design allows the same storage structure to support both fast transitions and reduced startup time without requiring separate complex structures for each function
Data Source
AI summary
A data processor includes a memory controller and a physical interface circuit coupled to the memory controller. In response to a system startup, the memory controller controls the physical interface circuit to selectively train a memory based on whether a first memory clock frequency of a plurality of power states equals any other memory clock frequency of the plurality of power states.