Controller Training Offset for Nonvolatile Memory Synchronization

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Solution Overview

Problem

In semiconductor memory systems, when multiple memory devices are controlled by a single controller, shared data input and output lines lead to sequential training, resulting in delays during power-on and readiness, as memory devices cannot be trained simultaneously.

Innovation Solution

A controller performs a first training operation with one nonvolatile memory device to detect offset information, which is then used to adjust delays for subsequent memory devices, allowing for simultaneous training and reducing power-on delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If data input and output lines are shared among multiple memory devices, then device complexity is reduced, but training must be performed sequentially resulting in increased power-on delay

Engineering Contradiction:
Improvecontroller structureVSAvoidpower-on delay
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The controller performs a first training operation with a first memory device before controlling second memory devices. By preliminarily obtaining offset information from the first memory device, the controller can pre-calculate and apply appropriate delays to data transmitted to subsequent memory devices, enabling synchronized training without sequential waiting

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The controller dynamically adjusts data transmission delays based on offset information obtained from different memory devices. By varying the delay applied to data for each memory device according to its specific offset characteristics, the system achieves simultaneous training readiness despite shared data lines

Inventive Principle:
Principle #15Dynamics

2Reliability

If memory devices are trained sequentially through shared data lines, then training reliability is improved, but productivity decreases due to extended training time

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidtraining speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The controller performs a first training operation to detect offset information from the first memory device, then uses this feedback to adjust and determine appropriate delays for subsequent memory devices. This feedback mechanism ensures reliable data transmission while enabling parallel training preparation

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

By preliminarily obtaining offset information through the first training operation, the controller prepares delay parameters in advance that can be applied to multiple memory devices simultaneously, transforming sequential training into a parallel-ready process that maintains reliability while improving productivity

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11238954B2Nonvolatile memory device, storage device including nonvolatile memory devices, and method of training data input and output lines between controller and nonvolatile memory devices
Publication Date: 2022.02.01 SAMSUNG ELECTRONICS CO LTD
  • US11238954B2 patent drawing
  • US11238954B2 patent drawing
  • US11238954B2 patent drawing

AI summary

A storage device includes a plurality of nonvolatile memory devices; and a controller connected in common to the plurality of nonvolatile memory devices through data lines, the controller being configured to detect first offset information by performing a first training operation with respect to a first nonvolatile memory device from among the plurality of nonvolatile memory devices, the controller being further configured to, based on the first offset information, perform a second training operation with respect to a second nonvolatile memory device from among the plurality of nonvolatile memory devices.