Memory Processing with Merged Address Translation for Lower TLB Latency
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Solution Overview
Problem
Existing memory address translation and transaction merge processes in computer systems suffer from latency and inefficiencies, particularly due to TLB misses and table walks, which degrade performance in applications like databases and virtual machines.
Innovation Solution
A memory processing system that simultaneously performs memory transaction merge and address translation by combining multiple transactions with the same page into a single transaction and using a TLB, table walk unit, and main page table to enhance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory transaction merge is performed separately from address translation, then transaction processing is simplified, but latency increases due to sequential processing
Solution Approach 1:
The patent combines memory transaction merge and address translation into a single unified process executed by the table walk unit. Multiple transactions sharing the same page are merged and translated simultaneously, eliminating the need for separate processing stages. This integration allows the system to perform both functions in parallel rather than sequentially, reducing overall latency while maintaining processing simplicity through a unified architectural approach.
Solution Approach 2:
The unified process ensures continuous useful action by eliminating idle periods between transaction merging and address translation. While traditional separate processing would complete merging then wait for translation, the integrated approach maintains continuous productive work flow, keeping the table walk unit actively processing transactions without interruption or idle cycles between distinct processing stages.
2Measurement precision
If address translation is performed for each transaction individually, then translation accuracy is maintained, but processing efficiency decreases
Solution Approach 1:
The patent merges multiple transactions that reference the same page into a single unified translation operation. Instead of performing identical address translations repeatedly for each transaction, the system consolidates them into one translation process. This maintains full translation accuracy for each individual transaction while dramatically improving processing efficiency by eliminating redundant translation operations. The unified process ensures that each transaction receives accurate translation while the bulk operation achieves high throughput.
3Speed
If TLB size is increased to reduce misses, then translation speed improves, but hardware cost and complexity increase
Solution Approach 1:
The patent performs preliminary action by merging transactions and performing address translation during the table walk process before transactions are fully processed. By anticipating the need for translation and executing it as part of the merge operation, the system reduces the frequency of TLB accesses. This approach maintains high translation speed by preparing translations in advance during natural table walk operations, while avoiding the hardware complexity of significantly enlarging the TLB structure.
4Measurement precision
If table walk is performed frequently to handle TLB misses, then translation accuracy is maintained, but system performance degrades
Solution Approach 1:
The patent combines multiple transactions requiring table walks into a single unified table walk operation. Instead of performing individual table walks for each TLB miss, the system merges the table walk requests and executes them collectively. This maintains full translation accuracy by ensuring each transaction receives proper page table lookup while dramatically improving system performance by reducing the total number of table walk operations. The unified approach eliminates redundant table walk overhead and improves overall throughput.
Data Source
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AI summary
A memory processing system (100) includes a processor (10), a main memory (20), and a MMU (30) coupled to the processor (10) and the main memory (20) . The processor (10) is used to generate a plurality of virtual addresses. The main memory (20) includes a plurality of data corresponding to physical addresses in a main page table (22) . The main page table (22) is used to map the plurality of virtual addresses to the plurality of physical addresses. The memory management unit (30) includes a TLB (32) coupled to the processor (10) and the main memory (20), a table walk unit (34) coupled to the TLB (32) and the main memory (20), and a merger (36) coupled to the TLB (32) and the processor (10). The TLB (32) performs address translation by retrieving a physical address according to a virtual address from a first page table in the TLB (32) or a second page table in the table walk unit (34) or the main page table (22) in the main memory (20) .