High-Voltage Memory Transceiver Using Native NMOS to Cut Power
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Solution Overview
Problem
Existing high voltage generation and transceiver circuits in non-volatile memory systems consume significant amounts of power, necessitating an improvement to reduce power consumption.
Innovation Solution
The use of a transceiver comprising a PMOS transistor and a native NMOS transistor, or a combination of PMOS, NMOS, and native NMOS transistors, to generate and manage high voltages for erase or program operations in non-volatile memory systems, incorporating features like high input-output isolation and voltage trimming to optimize power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If existing high voltage generation and transceiver circuits are used in non-volatile memory systems, then high voltages can be provided for erase or program operations, but power consumption is significant
Solution Approach 1:
The patent changes the electrical parameters of the transceiver circuit by using a native NMOS transistor instead of a conventional NMOS transistor. The native NMOS has different threshold voltage characteristics that allow it to operate efficiently at high voltages while consuming less power. This parameter change in the transistor type directly reduces power consumption during high voltage generation and transmission operations
Solution Approach 2:
The patent introduces a boot strap circuit as an intermediary mechanism to generate the high gate voltages required to turn on the native NMOS transistor. This boot strap circuit acts as a mediator that converts lower voltages into the necessary high gate voltages, enabling the native NMOS to function as a high voltage switch without requiring a separate high voltage power supply, thereby reducing overall power consumption
2Adaptability or versatility
If high voltage transceiver circuits are integrated into non-volatile memory chips, then erase and program operations can be performed, but chip area increases
Solution Approach 1:
The transceiver circuit is designed to perform multiple functions: it acts as both a high voltage output driver during programming operations and a high voltage input buffer during sensing operations. The same native NMOS transistor and boot strap circuit are reused for both transmit and receive functions, eliminating the need for separate dedicated circuits and reducing overall chip area
Solution Approach 2:
The patent combines the high voltage generation, transmission, and sensing functions into a single integrated transceiver unit. The output driver and input buffer share common circuit elements including the native NMOS transistor, boot strap circuitry, and control logic, merging multiple functions that would traditionally require separate circuits into one compact unit
3Ease of manufacture
If conventional NMOS transistors are used for high voltage switching, then the circuit can be manufactured with standard processes, but power consumption increases due to threshold voltage limitations
Solution Approach 1:
The patent changes the threshold voltage parameter by using a native NMOS transistor that has a threshold voltage close to zero, unlike conventional NMOS transistors that require higher gate voltages to turn on. This parameter change allows the transistor to conduct high currents with minimal gate voltage, significantly reducing power consumption while remaining compatible with standard CMOS manufacturing processes
Data Source
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AI summary
Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed. In one embodiment, a transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, a transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.