Memory Transfer Controller for Sound Decoder Chip Area Reduction
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Solution Overview
Problem
The increasing number of encoding methods for sound data in DVD players necessitates larger chip areas for embedded memory in sound decoders, leading to increased costs and potential processing speed reductions due to cache misses during pre-fetch operations.
Innovation Solution
A data processing integrated circuit with a CPU, memory, and a memory transfer controller that allows data to be transferred between external and internal memory, reducing the need for large internal memory capacity by storing programs and data in external memory and using SRAM for decoding operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the capacity of embedded memory is increased to store programs and data for multiple encoding methods, then the sound decoder can handle more encoding formats, but the chip area becomes larger thus increasing costs
Solution Approach 1:
The patent divides memory into two segments: embedded memory (small capacity) within the sound decoder chip and external memory (large capacity) outside the chip. The embedded memory stores only essential data for current decoding operations, while external memory stores programs and data for multiple encoding methods. This segmentation allows the sound decoder to support multiple encoding formats without increasing chip area, as the bulk storage is offloaded to external memory.
Solution Approach 2:
The patent extracts large-capacity storage functionality from the sound decoder chip to external memory. By taking out the need for large embedded memory and replacing it with a combination of small embedded memory and external memory, the chip area is reduced while still providing access to programs and data for multiple encoding methods through the external memory interface.
2Productivity
If pre-fetch is performed from external memory to cache memory, then data can be loaded in advance, but cache misses still occur reducing processing speed
Solution Approach 1:
The patent implements preliminary action by having the CPU predict which data will be needed in the future and loading it from external memory to embedded memory in advance. The read address storing section stores addresses of data to be used at later stages, enabling the system to proactively fetch data before it is actually needed, thus avoiding cache misses and maintaining continuous processing without interruption.
Data Source
AI summary
A data processing integrated circuit comprises a CPU, a memory that stores a program for controlling the CPU, a memory transfer controller for sending/receiving data to/from an external memory provided external to the data processing integrated circuit, and a read address storing section into which an address of data in the external memory is set by the CPU controlled by the program stored in the memory, which data is to be used at a later stage than a process being executed by the CPU, wherein the memory transfer controller transfers the data stored at the address in the external memory to the memory.