Heterogeneous Memory Data Transfer Pipelining

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Data transfers between heterogeneous memory arenas in computer systems are resource intensive due to the need for sequential data movement through multiple memory components, leading to increased latency and inefficiency.

Innovation Solution

The approach involves dividing data chunks into smaller portions and using pipelining to perform parallel copies between intermediate memory arenas, allowing independent DMA engines to work concurrently and optimize data transfers by overlapping execution steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is transferred sequentially through multiple memory arenas, then data transfer reliability is maintained, but data transfer time increases and productivity decreases

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoiddata transfer speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides a large data chunk into multiple smaller data portions or chunks. This segmentation allows the data transfer process to be broken down into multiple independent transfer operations that can be executed in parallel through different memory arenas, thereby reducing overall transfer time while maintaining data integrity through systematic error handling and verification at each segment level.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-processing data into manageable chunks, pre-establishing transfer pathways through intermediate memory arenas, and preparing error handling mechanisms before the actual data transfer begins. This includes setting up the pipeline structure and pre-allocating resources needed for parallel transfer operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 3:

The patent implements continuous data transfer by establishing a pipeline where multiple data chunks are transferred through different memory arenas simultaneously and continuously. Once a chunk is transferred to an intermediate arena, the next chunk immediately follows, eliminating idle time and ensuring continuous utilization of transfer resources, thereby maximizing productivity without compromising reliability.

Inventive Principle:
Principle #20Continuity of useful action

2Productivity

If data is divided into smaller portions and transferred in parallel, then data transfer productivity increases, but system complexity increases

Engineering Contradiction:
Improvedata transfer speedVSAvoidtransfer system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces intermediate memory arenas as mediators in the data transfer process. These intermediate arenas serve as buffer zones that simplify the complexity by providing standardized interfaces between different memory domains. Each intermediate arena handles specific transfer operations independently, reducing the overall system complexity while enabling parallel transfer operations that improve productivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

By segmenting data into smaller portions and organizing them for parallel transfer through dedicated intermediate arenas, the patent reduces the complexity of managing large data transfers. Each segment can be handled independently with its own error checking and verification, making the overall system more manageable and less complex than attempting to transfer large monolithic data blocks through a single pathway.

Inventive Principle:
Principle #1Segmentation

3Productivity

If multiple intermediate memory arenas are used for data transfer, then data transfer efficiency improves, but resource consumption increases

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidmemory resource usage
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent segments data into smaller chunks that can be distributed across multiple intermediate memory arenas for parallel transfer. This segmentation allows efficient utilization of available memory resources by dividing the transfer workload, improving overall transfer efficiency while preventing any single memory arena from being overloaded, thus optimizing resource consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs partial action by transferring data in portions rather than all at once through a single pathway. Multiple intermediate memory arenas are utilized partially and concurrently for different data chunks, which improves transfer efficiency by keeping memory resources actively engaged without requiring all resources to be fully allocated simultaneously, thereby optimizing the balance between efficiency and resource consumption.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9971710B2Optimizing data transfers between heterogeneous memory arenas
Publication Date: 2018.05.15 MICROSOFT TECHNOLOGY LICENSING LLC
  • US9971710B2 patent drawing
  • US9971710B2 patent drawing
  • US9971710B2 patent drawing

AI summary

Embodiments are directed to optimizing data transfers between heterogeneous memory arenas. In one scenario, a computer system receives an indication that a data chunk is to be transferred from a first memory arena to a third memory arena, and then determines that for the data chunk to be transferred from the first memory arena to the third arena, the data chunk is to be transferred from the first memory arena to a second memory arena, and from the second memory arena to the third memory arena. The computer system divides the data chunk into smaller data portions and copies a first data portion from the first memory arena to the second memory arena. The computer system then copies the first data portion from the second memory arena to the third memory arena and copies a second data portion from the first memory arena to the second memory arena in parallel.