Semiconductor Memory Transfer Switch Defective Current Control
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Solution Overview
Problem
Semiconductor memory devices with precharged sense amplifiers and bit lines at the same potential face increased power consumption due to defective currents flowing through sense amplifiers, especially when word lines and bit lines are shortcircuited, and existing solutions either increase complexity or slow down sense operations.
Innovation Solution
Implementing a control method that sets the transfer switch between the sense amplifier and bit lines to the off state before data writing or reading, and turning it on during data access, eliminating the need for a current limit element in the precharge circuit and allowing precharging at the same potential, thereby minimizing defective currents and enabling high-speed sense operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the transfer switch is kept in the on state to enable precharging of the sense amplifier and bit lines at the same potential, then the sense operation speed is improved, but a defective current continues to flow through the sense amplifier when the word line and bit line are shortcircuited
Solution Approach 1:
The transfer switch is made dynamically controllable with two states: turned on during the precharge period to enable fast sense operations, and turned off during the non-access period to block defective current. The control circuit adjusts the switch state based on the operational phase, resolving the contradiction between speed and energy loss.
2Loss of energy
If a current limit element is added to the bit line precharge circuit to decrease defective current, then the defective current is reduced, but a P-channel MOS transistor in the sense amplifier is slightly turned on, causing a defective current via the sense amplifier
Solution Approach 1:
The current limit element is extracted from the precharge circuit and replaced by controlling the transfer switch. Instead of adding a current limiting component, the solution removes the need for such an element by using the transfer switch to block defective current, thereby reducing device complexity while achieving the same goal.
3Loss of energy
If the transfer switch is set in the off state during the non-access period to block defective current, then defective current does not flow to the sense amplifier, but the control becomes complex and the sense operation becomes slow
Solution Approach 1:
The transfer switch is turned on in advance during the precharge period, which occurs before the actual sense operation. This preliminary action ensures that the sense amplifier and bit lines are precharged to the same potential, enabling fast sense operations without requiring complex control during the critical sense period.
4Loss of energy
If the transfer switch is turned off to block defective current, then power consumption is reduced, but the occupied area increases due to the need for additional control circuitry
Solution Approach 1:
The transfer switch serves multiple functions: it enables fast sense operations by allowing precharging of the sense amplifier and bit lines at the same potential, and it blocks defective current during the non-access period. This multi-functionality reduces the need for additional dedicated components, thereby minimizing the occupied area while achieving both speed and power consumption goals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces defective currents through the sense amplifier, maintains high-speed sense operations, and minimizes occupied area by eliminating the need for a current limit element in the precharge circuit.
Implementation Method 1
a transfer switch provided between the sense amplifier and the pair of bit lines
Implementation Method 2
a precharge circuit that precharges the sense amplifier and the pair of bit lines at the same potential
Data Source
AI summary
A semiconductor memory device includes a sense amplifier SA, a pair of bit lines BLT, BLB, a transfer switch SW provided between the sense amplifier SA and the pair of bit lines BLT, BLB, a precharge circuit PC that precharges the sense amplifier SA and the pair of bit lines BLT, BLB at the same potential, and a control circuit CTL. The control circuit CTL sets the transfer switch SW in the off state in the state before data is written or read, and turns on the transfer switch SW when writing or reading data via the pair of bit lines BLT, BLB. With this arrangement, a defective current flowing to the sense amplifier SA can be decreased, even when a word line WL and a bit line BL are shortcircuited.