Memory Transistor Structure With Butted Contacts for Lower Resistance
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Solution Overview
Problem
As semiconductor geometries shrink below ten atomic layers, there is a physical limit to miniaturization, hindering further integration density improvements in electronic components, and existing technologies face challenges in efficiently routing source/drain structures and reducing resistance/impedance in memory devices.
Innovation Solution
The implementation of a memory device design with gate-all-around transistors and single-dimensional butted contacts that reduce footprint area and enhance electrical connectivity, allowing for improved routing of source/drain structures and reduced resistance, enabling efficient data storage and retrieval without the need for deep vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If continuous reduction in minimum feature size is implemented, then integration density is improved, but physical limits of miniaturization are reached
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional FinFET structures with vertical channels. The channel extends vertically along the fin structure, adding a vertical dimension to current flow and gate control, thereby increasing integration density without further reducing lateral feature sizes
2Quantity of substance
If gate structures are miniaturized to increase integration density, then more transistors fit in smaller area, but gate control over channel becomes difficult
Solution Approach 1:
The FinFET structure creates a three-dimensional channel where the gate wraps around the channel on three sides (front, back, and sidewalls). This vertical fin structure provides superior gate control over the channel compared to planar structures, enabling precise control even at scaled dimensions
Solution Approach 2:
The gate structure is positioned within and surrounds the vertical fin channel structure. The gate electrode is nested within the dielectric layer that encapsulates the fin, creating a wrap-around configuration that enhances control authority
3Reliability
If source/drain structures are routed in traditional multi-dimensional paths, then connectivity is achieved, but resistance and impedance increase
Solution Approach 1:
The source and drain structures are formed as vertically extending fins rather than planar regions. Current flows vertically through the fin structures, creating shorter and more direct current paths that reduce resistance and impedance compared to traditional lateral routing
4Reliability
If deep vias are used to route source/drain structures, then connectivity is achieved, but device footprint area increases
Solution Approach 1:
The patent eliminates the need for deep vias by forming source and drain structures as vertically extending fins that provide direct vertical current paths. This removes the requirement for additional vertical interconnect structures, thereby minimizing the device footprint area while maintaining connectivity
Data Source
AI summary
A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.