Nonvolatile Memory Transistor Structure for Integration Density
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Solution Overview
Problem
The increasing number of switch transistors in three-dimensional nonvolatile semiconductor memory devices hinders the advancement of integration level due to their complexity and area occupation, limiting the memory capacity and efficiency.
Innovation Solution
The implementation of a transistor structure with a base insulating layer featuring trenches and a semiconductor layer that extends along the surface, allowing for a larger channel length and reduced chip area, along with a gate electrode layer connected over multiple channel semiconductor layers to minimize the number of upper layer wirings and contact plugs, thereby optimizing the integration level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of switch transistors is increased to support higher memory capacity, then the memory capacity is improved, but the device complexity and chip area increase, hindering integration level advancement
Solution Approach 1:
Multiple gate electrode layers (first gate electrode layer and second gate electrode layer) are merged to control a single channel semiconductor layer, allowing one transistor structure to perform the function of multiple transistors. This merging approach reduces the total number of transistor components needed while maintaining the ability to control multiple word lines, thereby improving memory capacity without proportionally increasing device complexity
Solution Approach 2:
The patent transitions from a planar transistor arrangement to a three-dimensional stacked structure where gate electrode layers are positioned at different heights (first gate electrode layer at first height, second gate electrode layer at second height) to control the same channel semiconductor layer. This vertical dimensionality change allows multiple gate controls to be achieved within a compact footprint, reducing chip area while supporting higher memory capacity
2Ease of operation
If traditional transistor structures are used with separate gate controls for each word line, then each word line can be independently controlled, but the chip area occupied by word line connection circuits increases
Solution Approach 1:
Multiple gate electrode layers are merged to share a common channel semiconductor layer, allowing independent control of multiple word lines through vertically stacked gates rather than requiring separate lateral transistor structures. This merging eliminates the need for multiple separate transistor instances, significantly reducing the chip area occupied by word line connection circuits while preserving independent word line control capability
Solution Approach 2:
The control structure moves from a lateral arrangement where each word line control would require separate transistor instances occupying planar area, to a vertical stacked arrangement where multiple gate electrode layers are positioned at different heights. This dimensional transition enables independent word line control without proportionally increasing chip area, as the control elements are stacked vertically rather than spread laterally
Data Source
AI summary
This nonvolatile semiconductor memory device includes: a memory cell array including a memory cell; a wiring part connecting the memory cell array to an external circuit; and a transistor that connects the wiring part and the external circuit, the transistor including: a first insulating layer including a first region, a second region, and a third region, the second and third regions being disposed on both sides of the first region, and a height of an upper surface of the first region being lower than those of the second region and the third region; a semiconductor layer disposed along upper surfaces of the first region, the second region, and the third region; and a gate electrode layer disposed via the semiconductor layer and a gate insulating film, on an upper part of the second region.