Memory Transistor Curing Using GIDL Joule Heating
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Solution Overview
Problem
Existing nonvolatile memory devices, such as flash memories, suffer from reliability degradation due to interface traps and fixed charges at the bonding interface between the channel and tunnel insulating layer, which are exacerbated by frequent write and erase operations, and current methods like wafer-scale global annealing are costly, require additional equipment, and can cause thermal damage.
Innovation Solution
A method involving gate-induced drain leakage (GIDL) current is used to generate Joule heating, allowing for selective and localized curing of memory transistors at the unit device level, removing interface traps and fixed charges without additional equipment or excessive power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer-scale global annealing process is used to remove interface traps and fixed charges, then reliability of memory device is improved, but manufacturing cost increases due to furnace equipment and high power consumption
Solution Approach 1:
The patent divides the annealing process into two stages: first, a rapid thermal annealing process is applied to the entire wafer to remove interface traps; second, a lower-temperature annealing process is applied selectively to specific regions or devices that require additional treatment. This segmentation allows the use of simpler, more cost-effective equipment while achieving the same reliability improvement as full wafer-scale annealing.
Solution Approach 2:
The patent implements local quality by applying different annealing temperatures and durations to different regions of the wafer based on their specific requirements. Devices or regions with severe interface trap accumulation receive more intensive treatment, while others receive sufficient but less intensive treatment. This localized approach reduces overall power consumption and equipment requirements while maintaining high reliability where needed.
2Reliability
If wafer-scale global annealing process is applied, then interface traps are removed, but thermal damage occurs in regions that do not require additional annealing
Solution Approach 1:
The annealing process is segmented into a first rapid thermal annealing step that removes interface traps from the entire wafer, followed by a second selective annealing step that applies heat only to specific regions or devices requiring additional treatment. This prevents unnecessary thermal exposure to regions that have already been adequately treated, avoiding thermal damage while maintaining reliability improvement where needed.
Solution Approach 2:
The patent employs periodic action by applying annealing treatment in distinct phases: an initial rapid thermal annealing phase followed by selective annealing phases for specific regions. This periodic application of heat allows interface traps to be removed effectively while limiting cumulative thermal exposure in any given region, thereby preventing thermal damage.
3Reliability
If global annealing process is used, then reliability is improved, but the process cannot be applied at unit chip or unit device scale in delivered products
Solution Approach 1:
The patent segments the annealing process into a universal first step (rapid thermal annealing) that can be applied to entire wafers during manufacturing, and a second step that can be applied selectively at unit chip or unit device scale even in delivered products. This segmentation enables the technology to be implemented flexibly across different production stages and scales, including post-delivery applications.
Solution Approach 2:
The patent utilizes parameter changes by adjusting annealing temperature, duration, and spatial distribution to match the scale and requirements of the application. For unit chip or unit device scale applications in delivered products, the parameters are optimized to achieve effective interface trap removal with minimal thermal impact, enabling versatility across different application scenarios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively improves the reliability and performance of nonvolatile memory devices by selectively curing transistors at low cost, maintaining device layout and enabling application in unit chip or unit device scale, even after delivery.
Implementation Method 1
curing the memory transistor by generating a gate induced drain leakage (GIDL) current on a drain side of the memory transistor and using Joule heating caused by the GIDL current
Data Source
AI summary
A nonvolatile memory device and an operating method thereof are disclosed. An operating method of a nonvolatile memory device may comprise providing the nonvolatile memory device including a memory transistor, the memory transistor including a source, a drain, a channel disposed between the source and the drain, and a first insulating layer, a charge storage layer, a second insulating layer, and a gate which are sequentially disposed on the channel, and curing the memory transistor by removing charges or traps existing at least at an interface between the channel and the first insulating layer by generating a gate induced drain leakage (GIDL) current on the drain side of the memory transistor and using Joule heating caused by the GIDL current.