3D Memory Device Local Global Transistor Placement
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Solution Overview
Problem
The increasing number of pass transistors and routing circuitry in stacked memory arrays leads to larger memory device sizes, making it challenging to maintain memory density and efficiency in three-dimensional memory devices.
Innovation Solution
The configuration of local and global devices at substantially the same level above stacked tiers of memory cells, where local devices provide selective access to data lines and global devices access global lines, reducing the need for pass transistors and routing circuitry complexity by shortening local access lines and relocating pass transistors above the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked memory arrays are used to increase memory density, then memory capacity is improved, but device size increases due to more pass transistors and routing circuitry
Solution Approach 1:
The patent relocates pass transistors from the traditional bottom-periphery region to the top-periphery region above the memory array. This vertical redistribution allows the same functional elements to occupy different spatial dimensions, enabling the memory array to expand vertically while keeping the footprint area manageable.
Solution Approach 2:
The patent segments the device into distinct functional regions: memory cells in the bulk, local access lines at intermediate levels, pass transistors at the top periphery, and routing circuitry distributed throughout. This segmentation allows each component to be optimized independently and reduces overall device size by eliminating redundant routing paths.
2Productivity
If more pass transistors are added to access more memory cells in stacked arrays, then memory access capability is improved, but current leakage and voltage stress on pass transistors increase
Solution Approach 1:
The patent introduces local access lines at intermediate vertical levels between the memory cells and the pass transistors. These local access lines provide dedicated access paths for each memory cell tier, isolating the electrical signals and reducing current leakage between different levels. The pass transistors only need to switch between local access lines rather than directly between global lines, reducing voltage stress.
3Adaptability or versatility
If routing circuitry is extended to connect pass transistors to global access lines in stacked arrays, then connectivity is improved, but device complexity increases
Solution Approach 1:
The patent merges the local access lines with the global access lines at the top periphery, where both types of lines coexist and share the same routing infrastructure. This merging eliminates the need for separate routing paths for local and global connections, significantly simplifying the overall routing circuitry while maintaining full connectivity.
Data Source
AI summary
In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.