Nonvolatile Memory Speed via Low Voltage Transistor Segmentation
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Solution Overview
Problem
The operation speed of nonvolatile semiconductor memory devices is insufficient due to the use of high withstand voltage transistors, which result in smaller drive currents and difficulties in quickly reading information from memory cell transistors.
Innovation Solution
The implementation of low voltage transistors with thinner gate insulation films as sector select transistors and voltage application units, allowing for larger read currents and faster information retrieval by controlling electric potentials and voltages applied to different wells and transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high withstand voltage transistors are used in nonvolatile semiconductor memory devices, then reliability is improved, but operation speed deteriorates due to smaller drive currents
Solution Approach 1:
The patent divides the transistor population into two segments: high withstand voltage transistors for reliability-critical functions (memory cell transistors, voltage application units) and low voltage transistors for speed-critical functions (sector select transistors, row decoder, column decoder). This segmentation allows each segment to be optimized for its specific requirement without compromising the other.
Solution Approach 2:
Different transistor types are assigned to different locations within the device based on functional requirements. Low voltage transistors with thinner gate insulation films are placed in the row decoder, column decoder, and sector select transistor positions where high drive current is needed, while high withstand voltage transistors are used in memory cell and voltage application unit positions where reliability is paramount.
2Speed
If low voltage transistors with thinner gate insulation films are used, then operation speed is improved through larger drive currents, but reliability deteriorates due to reduced voltage withstand capability
Solution Approach 1:
The patent segments transistors into low voltage types for speed-critical areas (row decoder, column decoder, sector select transistors) and high withstand voltage types for reliability-critical areas (memory cell transistors, voltage application units), allowing each to operate in its optimal performance zone.
Solution Approach 2:
Low voltage transistors with thinner gate insulation films are strategically placed only in locations where high drive current is required and voltage stress is controlled (decoder circuits and sector select transistors), while high withstand voltage transistors are used where voltage stress is high and reliability is critical.
3Strength
If high withstand voltage transistors are used throughout the device, then voltage stress resistance is improved, but read current magnitude deteriorates leading to slower information retrieval
Solution Approach 1:
The patent segments the device into voltage stress-critical regions (memory cells, voltage application units) using high withstand voltage transistors and current-critical regions (decoders, sector select transistors) using low voltage transistors with higher drive currents.
Solution Approach 2:
Low voltage transistors are placed locally in the row decoder, column decoder, and sector select transistor positions where large drive currents are needed to quickly charge/discharge capacitor nodes and switch bit lines, while high withstand voltage transistors are used where voltage stress resistance is the primary requirement.
Data Source
AI summary
A nonvolatile semiconductor memory device including a first bit line commonly coupling drain sides memory cells; a word line commonly coupling control gates of memory cell transistors; a column decoder coupled to a second bit line; a row decoder coupled to a word line; a first transistor having a source coupled to the first bit line and having a drain electrically coupled to the column decoder via the second bit line; and a first control unit for controlling potential of a gate of the first transistor, the memory cell transistor being formed over a first well, the first transistor being formed over a second well electrically isolated from the first well, a film thickness of a gate insulation film of the first transistor being smaller than that of a gate insulation film of a second transistor formed in the row decoder and coupled to the word line.