Stacked Memory Transistor Oxide Structure for Trap Center Suppression
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Solution Overview
Problem
Semiconductor devices with stacked memory cells face issues due to trap centers formed at the interface between semiconductor and insulator, affecting on-state current, field-effect mobility, and reliability.
Innovation Solution
A semiconductor device with a memory transistor structure that includes a conductor with an opening, multiple insulators, and oxides with varying energy gaps, where the second oxide has a narrower energy gap than the first oxide, and specific atomic ratios of elements like In, Ga, and Zn, to suppress the formation of trap centers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If semiconductor is in direct contact with insulator to simplify structure, then device complexity is reduced, but trap centers form at interface causing deterioration of electrical characteristics
Solution Approach 1:
A first oxide layer is introduced as an intermediary between the semiconductor and the insulator. This intermediate oxide layer prevents direct contact between the semiconductor and insulator, thereby suppressing trap center formation at the interface while maintaining structural simplicity. The oxide layer acts as a buffer that eliminates harmful interface effects without adding complex multi-layer structures.
2Reliability
If multiple oxides with different energy gaps are stacked to suppress trap centers, then reliability is improved, but device complexity increases
Solution Approach 1:
Different oxide layers with specific energy gap characteristics are positioned at specific locations between the semiconductor and insulator. The first oxide has a narrower energy gap to suppress trap centers, while a second oxide with a wider energy gap is positioned adjacent to it. This localized differentiation of material properties at specific interfaces optimizes trap center suppression without requiring complex multi-layer structures throughout the entire device.
3Quantity of substance
If stacking memory cells is implemented to increase storage capacity, then storage capacity per unit area is improved, but trap center formation at semiconductor-insulator interface adversely affects on-state current and field-effect mobility
Solution Approach 1:
In stacked memory cell structures, a first oxide layer with narrower energy gap is introduced as an intermediary between the semiconductor and the insulator (tunnel dielectric or charge accumulation layer). This intermediate oxide suppresses trap center formation that would otherwise occur at the direct semiconductor-insulator interface, thereby preserving high on-state current and field-effect mobility while enabling increased storage capacity through vertical stacking.
Solution Approach 2:
The energy gap parameter of the oxide layer is specifically optimized to be narrower than that of the adjacent oxide or insulator material. This parameter change in the oxide's energy gap creates favorable band alignment that suppresses trap center formation, enabling the semiconductor device to maintain high electrical characteristics while implementing stacked memory cell architecture for increased storage density.
Data Source
AI summary
A semiconductor device having a large storage capacity per unit area is provided. The semiconductor device includes a memory transistor. The memory transistor includes a conductor including an opening, a first insulator provided in contact with an inner side of the opening, a second insulator provided in contact with an inner side of the first insulator, a third insulator provided in contact with an inner side of the second insulator, a first oxide provided in contact with an inner side of the third insulator, and a second oxide provided in contact with an inner side of the first oxide. An energy gap of the second oxide is narrower than an energy gap of the first oxide.