Memory Address Translation LUT for Low-Latency NVMe Caching
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Solution Overview
Problem
Existing address translation methods in memory devices, such as those using content-addressable memory (CAM), face limitations in capacity and impractical gate counts, and require host device involvement for entry invalidation, leading to inefficiencies and high latency.
Innovation Solution
Implementing a lookup table (LUT) for address translation, where an index (LUT ID) is used to retrieve translated addresses, allowing the address translation cache (ATC) to make translation requests independently, reducing latency and hiding translation operations from NVMe control circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If content-addressable memory (CAM) is used for address translation, then address translation capacity is improved, but gate count becomes impractically high
Solution Approach 1:
The patent segments the address translation function into two parts: a small CAM for storing translation cache entries (TCEs) and a LUT for storing the mapping between virtual addresses and TCE indices. This segmentation allows the system to achieve high address translation capacity without requiring a large CAM, thus reducing gate count while maintaining functionality.
Solution Approach 2:
The patent introduces an intermediate structure (LUT - Lookup Table) that mediates between the virtual address and the CAM. Instead of directly mapping all virtual addresses to physical addresses in a large CAM, the LUT provides an intermediate indexing layer that reduces the burden on the CAM size and complexity.
2Reliability
If host device involvement is required for ATC entry invalidation, then address translation reliability is improved, but translation latency increases
Solution Approach 1:
The ATC is designed to invalidate its own entries autonomously without requiring host device involvement. When a TCE needs to be invalidated, the ATC detects this condition and performs the invalidation operation itself, eliminating the latency associated with host device communication while maintaining translation reliability.
3Measurement precision
If address translation operations are exposed to NVMe control circuitry, then translation accuracy is improved, but system complexity increases
Solution Approach 1:
The patent extracts the address translation operations from the NVMe control circuitry and implements them independently within the ATC. The ATC handles translation requests autonomously using its internal LUT and CAM structures, preventing complex translation operations from propagating to the NVMe control circuitry while maintaining accurate translation results.
Data Source
AI summary
Translated addresses of a memory device can be stored in a first LUT maintained by control circuitry. Untranslated addresses can be stored in a second LUT maintained by the control circuitry. In response to a translation request for a particular translated address of the memory device corresponding to a target untranslated address, an index of the second LUT associated with the target untranslated address can be determined, the index of the second LUT can be mapped to an index of the first LUT, and the particular translated address corresponding to the target untranslated address can be retrieved from the first LUT.