Memory Address Translation With Simple Arithmetic for CXL Data Recovery

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Solution Overview

Problem

Existing memory address translation methods require complex operations such as division, leading to substantial latency and resource exhaustion in memory systems, especially in compute express link (CXL) compliant systems.

Innovation Solution

Implement memory address translation using simpler arithmetic operations like addition and subtraction, eliminating the need for complex circuitries and reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If complex division operations are used for memory address translation, then data protection and recovery capabilities are improved, but latency increases and resources are exhausted

Engineering Contradiction:

Improvedata protection and recoveryVSAvoidlatency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the operational parameters of address translation by replacing division operations with addition and subtraction operations. This parameter change maintains the ability to translate host addresses to device addresses while significantly reducing the computational complexity and time required, thus resolving the contradiction between data protection capabilities and latency

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent extracts the essential function of address translation from complex division operations and implements it using simpler arithmetic operations. By taking out the unnecessary complexity while preserving the core functionality of mapping host addresses to device addresses for data protection, the system achieves both reliability and low latency

Inventive Principle:

Principle #2Taking out (Extraction)

2Reliability

If complex circuitries are implemented for address translation, then data protection capabilities are enhanced, but device complexity increases

Engineering Contradiction:

Improvedata protectionVSAvoidcircuitry complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces complex, resource-intensive division circuitry with simpler addition and subtraction circuitry. This substitution uses less complex, more efficient computational building blocks that achieve the same address translation function without requiring elaborate circuit designs, thus reducing device complexity while maintaining data protection capabilities

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent substitutes complex mechanical/computational operations (division) with simpler arithmetic operations (addition and subtraction) in the address translation process. This operational substitution reduces the complexity of the required circuitry while preserving the essential function of mapping addresses for data protection and recovery

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250328474A1Memory address translation for data protection and recovery

Publication Date: 2025.10.23 MICRON TECHNOLOGY INC

AI summary

Address translation of host commands to access host data stored in memory devices that provides a chip kill capability not only involves locating where the host data is stored, but also involves locating where parity data striped with the host data is stored. In locating where the parity data is stored, the address translation can be performed with logical (e.g., arithmetic) operations.