Semiconductor Memory Device Threshold Voltage Stabilization
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Solution Overview
Problem
Nonvolatile semiconductor memory devices with field effect transistors experience fluctuations in threshold voltage due to repeated erase operations, leading to reliability issues such as malfunctions in write and read operations.
Innovation Solution
A semiconductor memory device with a control circuit that performs specific voltage pulse operations, including write, erase, recovery, and charge removing operations, to manage the trap levels in the tunnel insulating layer, thereby stabilizing the threshold voltage and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repeated erase operations are performed on memory cells, then data storage capacity is maintained, but threshold voltage fluctuates and reliability deteriorates
Solution Approach 1:
A recovery operation is performed preliminarily before the threshold voltage fluctuation becomes problematic. The control circuit counts erase operations and executes a recovery operation when the count reaches a predetermined threshold, proactively preventing threshold voltage instability before it affects memory reliability
Solution Approach 2:
The invention changes the electrical parameters (voltage and time) of the recovery operation to actively manage trap levels. By applying a recovery voltage pulse with specific characteristics (different from normal read/write operations), the trap levels in the tunnel insulating layer are modified, thereby stabilizing the threshold voltage of the memory cell transistor
2Reliability
If recovery operation is performed to reduce trap levels, then threshold voltage stability improves, but additional operation time is required
Solution Approach 1:
Instead of continuous monitoring and recovery, the invention uses periodic action by counting erase operations and triggering a recovery operation only when the count reaches a predetermined threshold. This periodic intervention approach maintains threshold voltage stability while minimizing the total time spent on recovery operations
Solution Approach 2:
The recovery operation is performed preliminarily at predetermined intervals based on erase operation counting, preventing threshold voltage degradation before it occurs. This proactive approach at scheduled intervals is more efficient than reactive correction, as it prevents the need for more extensive recovery operations later
Data Source
AI summary
A semiconductor memory device of embodiments includes a semiconductor layer, a gate electrode layer, memory cells each including a gate insulating layer containing Si, O, and N, and a control circuit. The control circuit performs a write operation and an erase operation on the memory cells. The control circuit determine whether or not the number of times of execution of the erase operation on the memory cells has reached a predetermined number of times. When the number has reached the predetermined number of times, the control circuit perform first processing and second processing on the memory cells. The first processing applies a voltage with the same polarity as that in the write operation to the gate electrode layer with a pulse width larger than that in the write operation. The second processing applies a voltage with a polarity opposite to that in the write operation to the gate electrode layer.