Memory Allocator Tree Counters for Low-Latency Fragmented Storage

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Solution Overview

Problem

Existing free space allocators in large scale storage systems face challenges in maintaining low latency overhead while efficiently handling memory allocation requests, especially when memory space is highly fragmented.

Innovation Solution

A computing system utilizing a tree data structure with counter sets to manage non-volatile memory allocation, where each counter set indicates the number of unallocated blocks, allowing efficient allocation and release of memory space with low latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bitmap and range list methods are used to track free and allocated memory spaces, then memory allocation can be performed, but latency overhead increases and efficiency decreases when memory space is highly fragmented across large address spaces

Engineering Contradiction:
Improvememory allocation efficiencyVSAvoidlatency overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the large address space into multiple regions, and each region is further divided into blocks. This hierarchical segmentation allows the memory allocator to manage large address spaces by working with smaller, manageable units (blocks within regions), reducing the complexity and latency of tracking free space across the entire address space while maintaining allocation efficiency even when fragmentation occurs.

Inventive Principle:
Principle #1Segmentation

2Productivity

If traditional bitmap methods are used to track memory spaces, then allocation can be performed, but the system cannot maintain low latency overhead at massive scales

Engineering Contradiction:
Improveallocation speedVSAvoidlatency overhead
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent introduces a hierarchical dimension to memory management by organizing blocks into regions and creating a tree data structure with multiple levels. This dimensional organization transforms the flat bitmap approach into a multi-level structure, enabling faster allocation operations by operating at higher levels of the hierarchy when possible, thus maintaining low latency overhead even at massive scales.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The system pre-organizes memory blocks into regions and establishes the tree data structure hierarchy before allocation operations begin. This preliminary organization allows the memory allocator to quickly navigate and identify available blocks without performing complex searches during allocation, thereby maintaining low latency overhead while achieving high allocation speed.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If large address spaces are managed with traditional methods, then memory can be allocated, but efficiency decreases when free space is highly fragmented

Engineering Contradiction:
Improvememory management efficiencyVSAvoiddata structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

By segmenting the large address space into regions and further into blocks, the patent reduces the complexity of managing fragmented memory. Each region and block can be independently tracked with simple counters in the tree structure, avoiding the need for complex data structures to handle fragmentation across the entire address space, thus maintaining efficiency while managing complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4386566B1System and method for allocating memory space
Publication Date: 2026.02.18 LEMON INC(GB)
  • EP4386566B1 patent drawingFigure 1
  • EP4386566B1 patent drawingFigure 2
  • EP4386566B1 patent drawingFigure 3

AI summary

A system and method are described to efficiently allocate memory space with low latency overhead by allocating blocks of non-volatile memory on a storage device according to a tree data structure comprising a plurality of counter sets, each counter set including one or a plurality of counters indicating numbers of unallocated blocks of memory space within the non-volatile memory.