Memory Tree Tag Generation for Efficient Tamper Detection

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Solution Overview

Problem

Existing memory protection technologies using tree structures face inefficiencies in processing, particularly in parallel processing of hash generation and other operations, and require high-speed reading and writing capabilities.

Innovation Solution

A memory processing apparatus that allocates unique memory addresses to nodes in a tree structure, generates tags using a message authentication code (MAC) for each node, and updates tags incrementally, allowing for efficient verification and updating of memory contents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a tree structure is used for memory protection, then security against tampering is improved, but the processing amount for writing increases

Engineering Contradiction:
Improvememory protectionVSAvoidwriting speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides the memory protection process into segments: authentication tags are generated only for nodes that have changed (leaf nodes representing modified data blocks), rather than regenerating tags for the entire tree structure. This segmentation allows partial updates to maintain security while reducing processing overhead for writing operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by maintaining authentication tags for all nodes in advance. When a write operation occurs, the system only needs to update tags for affected nodes and their ancestors, rather than recalculating all tags from scratch. This preliminary preparation of tag structures enables faster write operations.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If traditional hash generation is used in tree structure, then security is maintained, but parallel processing cannot be performed

Engineering Contradiction:
ImprovesecurityVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The authentication tag generation process is segmented into independent operations for different nodes. Each node's tag can be generated independently using the same MAC function with different inputs (node identifier and data), allowing parallel computation across multiple nodes without interfering with each other's security properties.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameters of the hash generation function by using a message authentication code (MAC) instead of traditional hash functions. The MAC function takes additional parameters (node identifier, parent tag) that enable both security verification and parallel processing capabilities, as each node's computation remains independent and verifiable.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If authentication tags are generated for all nodes, then tampering detection is improved, but processing time increases

Engineering Contradiction:
Improvetampering detectionVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system applies different quality levels of tag generation to different nodes based on their importance and change frequency. Leaf nodes representing actual data blocks have full authentication tags, while intermediate nodes have tags that can be verified without full regeneration. This local differentiation maintains comprehensive tampering detection while reducing overall processing time.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The authentication tag structure is designed to be self-verifying through its hierarchical nature. Each node's tag inherently contains verification information for its parent nodes, allowing the system to verify tampering detection capability without externally regenerating all tags. The structure serves its own verification needs efficiently.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12328397B2Memory processing apparatus, memory verification apparatus, memory updating apparatus, memory protection system, method, and computer readable medium
Publication Date: 2025.06.10 NEC CORP
  • US12328397B2 patent drawing
  • US12328397B2 patent drawing
  • US12328397B2 patent drawing

AI summary

A memory address allocation unit allocates, to each of nodes in a tree structure configured for protecting a memory, a memory address unique to the node. A tag generation unit defines, for each of the nodes in the tree structure, a connection of the memory address and a constant as a nonce, and generates a tag by inputting the nonce and a plaintext of which tampering with is to be detected, or the nonce and a plurality of constants of child nodes of each of the nodes into a message authentication code, the message authentication code being a code by which a partially-updatable tag can be output. A node generation unit uses a constant as a local counter, and generates each of the nodes in the tree structure by combining at least a tag and the local counter.