Memory Tunneling Interface for DDR Access to Emerging Memory

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Solution Overview

Problem

Emerging memory technologies, such as FeRAM, MRAM, ReRAM, and phase-change memories, often have attributes that do not comply with standard memory interface requirements, making them difficult or impossible to be directly addressed by memory controllers, requiring costly redesigns and investments in new interface standards.

Innovation Solution

Implementing a register architecture and tunneling protocol that allows emerging memories to be accessed via a standard compliant DDR-DRAM interface using memory-mapped registers and tunneling protocol, enabling communication through existing DDR-DRAM protocols and hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If emerging memory technologies are used, then memory capacity and performance are improved, but compatibility with standard memory interfaces deteriorates

Engineering Contradiction:
Improvememory performanceVSAvoidinterface compatibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

A tunneling interface is introduced as an intermediary layer between the memory controller and emerging memory devices. This interface includes register structures that translate standard DDR-DRAM commands into device-specific operations, enabling compatibility without compromising the performance benefits of emerging memory technologies.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If memory controllers are redesigned to support emerging memories, then interface compatibility is improved, but manufacturing cost and complexity increase

Engineering Contradiction:
Improveinterface compatibilityVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The tunneling interface is designed to work with multiple types of emerging memory devices (FeRAM, MRAM, ReRAM, phase-change memories) through a unified register-based architecture. This universal approach allows existing memory controllers to support various emerging memory types without requiring device-specific redesigns, thereby reducing manufacturing costs and complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If new interface standards are developed, then compatibility with emerging memories is improved, but development time and investment increase

Engineering Contradiction:
Improveemerging memory compatibilityVSAvoiddevelopment time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The invention changes the interface parameters by using existing DDR-DRAM command structures and register formats rather than developing entirely new interface protocols. This parameter-based approach allows emerging memories to be accessed through standard interfaces by modifying only the register access patterns, significantly reducing development time and investment.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12524356B2Memory tunneling interface
Publication Date: 2026.01.13 SEAGATE TECH LLC
  • US12524356B2 patent drawing
  • US12524356B2 patent drawing
  • US12524356B2 patent drawing

AI summary

An apparatus may include a memory device, a memory controller, or both that can communicate via memory standard interfaces. However, the memory device may have physical memory that does not comply with the memory standard by itself. Disclosed herein are solutions that allow various non-standard types of memory, or emerging memory, to be utilized via a host, microprocessor, or memory controller that implements the interface standard. For example, by utilizing a command converter at the microprocessor and a tunneling register at the memory device, a microprocessor can send commands to the memory device by writing them to the tunneling register, which can then be processed at the memory device for operations to be performed with the non-standard or emerging memory.