Memory Turnaround Timing Optimization via Checksum Segmentation
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Solution Overview
Problem
Conventional approaches to providing data integrity and error detection in memory systems can compromise memory processing efficiency and overall system performance by accounting for the entire data frame, including error bit checksums, even though the checksum processing does not require DRAM core access, leading to unnecessary latency in back-to-back transactions.
Innovation Solution
Optimizing turnaround timing by defining the start of the turnaround time for successive transactions immediately after the transfer of data bits, excluding the time required for processing error bit checksums, thereby advancing the initiation of subsequent operations and reducing overall latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error bit checksum processing is included in the turnaround time for successive transactions, then data integrity is ensured, but transaction latency increases
Solution Approach 1:
The patent segments the data frame transmission into two independent parts: data bits and error bit checksums. The turnaround time for successive transactions is defined to begin immediately after the data bits are transferred, excluding the checksum processing time. This segmentation allows the checksum verification to occur in parallel without blocking subsequent transactions, thus resolving the contradiction between ensuring data integrity and minimizing transaction latency.
2Reliability
If turnaround time includes entire data frame processing, then error detection is completed, but processing efficiency decreases
Solution Approach 1:
The patent applies preliminary action by defining the turnaround time to begin before the error bit checksum processing is complete. Specifically, the turnaround time starts immediately after the data bits are transferred to the memory device, allowing subsequent transactions to be initiated while checksum verification is still in progress. This preliminary initiation of next transactions maintains error detection capability while improving processing efficiency by eliminating unnecessary waiting time.
Data Source
AI summary
Systems, methods, and apparatuses are directed to optimizing turnaround timing of successive transactions between a host and a memory device. The host includes framing logic that generates a write frame that includes a plurality of data bits and an error bit checksum that is appended at the end of the data bits. The host further includes a bus infrastructure configured to accommodate the transfer of the write frame to the memory device and logic that defines the turnaround time to begin at a time instant that immediately follows the transfer of the data bits of the write frame. The turnaround time measures the time delay at which a succeeding write frame is to be transferred. In this manner, the turnaround time is optimized to enable the earlier initiation of successive data operations, thereby reducing the overall latency of successive back-to-back transactions.