Memory Uncertainty Prediction Circuit for Data Integrity
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Solution Overview
Problem
Data stored in memory devices can become corrupted due to unexpected power loss or device shutdown, leading to inefficient storage usage when entire blocks are rendered unusable upon detecting incorrect data in a single row of memory cells.
Innovation Solution
A memory device with an uncertainty prediction circuit and data conversion circuits that determine the level of uncertainty in memory cell states, applying specific data conversions to affected data subsets while allowing other memory cells to continue storing original data, thereby improving storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire block is prevented from further use upon detecting a row of memory cells storing incorrect data, then data integrity is ensured, but storage efficiency deteriorates
Solution Approach 1:
The patent divides the memory block into multiple rows of memory cells and evaluates each row independently. When data corruption is detected in one row, only that specific row is marked as invalid while other rows remain usable. This segmentation approach prevents the cascading failure of the entire block, thereby maintaining storage efficiency while ensuring data integrity through selective invalidation.
2Reliability
If data conversion is applied to all memory cells, then data uncertainty is fully addressed, but processing complexity increases
Solution Approach 1:
The patent applies data conversion operations selectively based on the uncertainty level of individual memory rows. The uncertainty prediction circuit evaluates each row and triggers data conversion only for rows exhibiting signs of corruption. This localized application of data conversion reduces processing complexity compared to applying conversion to all memory cells, while still effectively addressing data uncertainty in affected areas.
Data Source
AI summary
The present disclosure is directed to a device, a method, and a non-transitory computer readable medium for determining a level of uncertainty of programmed states of memory cells. In one aspect, a memory device includes memory cells, an uncertainty prediction circuit coupled to the memory cells, and a data conversion circuit coupled to the memory cells. The uncertainty prediction circuit is configured to determine, from a subset of the memory cells coupled to a word line, a number of memory cells having a predetermined state. The data conversion circuit is configured to apply a data conversion to a portion of data stored by the subset of the memory cells, in response to the uncertainty prediction circuit determining that the number of memory cells is between a first threshold and a second threshold.