Semiconductor Memory Device With Unified Access Controller

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The challenge is to reduce the number of connection electrodes and package size in semiconductor memory devices while optimizing performance for accessing both main and storage memories in mobile devices, where existing solutions increase package size and manufacturing costs due to separate memory configurations.

Innovation Solution

A multi-chip package structure is implemented with an access controller that facilitates data communication between volatile and nonvolatile memories using different protocols, and a single host interface, reducing the number of external connection terminals and integrating main and storage memories within a single module.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If main memory and storage memory are packaged separately, then each memory can be optimized independently, but the package size and number of connection electrodes increase

Engineering Contradiction:
Improvememory optimizationVSAvoidpackage size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines main memory (volatile memory) and storage memory (non-volatile memory) into a single integrated memory device with a unified package structure. This merging reduces the total package size and number of connection electrodes while maintaining independent optimization capabilities for both memory types through separate memory controllers and interfaces within the same package.

Inventive Principle:
Principle #5Merging (Combining)

2Ease of operation

If multiple host interfaces are used for separate memory packages, then each memory can be accessed independently, but the number of connection electrodes and manufacturing cost increase

Engineering Contradiction:
Improvememory access independenceVSAvoidnumber of host interfaces
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent implements a universal host interface that can communicate with both volatile and non-volatile memories through a single interface structure. This multi-functional interface reduces the number of connection electrodes and simplifies the host connection architecture while maintaining the ability to independently access both memory types through protocol conversion and data routing mechanisms.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Area of stationary object

If a single integrated memory package is used, then the package size and connection electrodes are reduced, but protocol conversion and data communication complexity increase

Engineering Contradiction:
Improvepackage sizeVSAvoidprotocol conversion complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent introduces protocol conversion modules and data communication controllers as intermediary components within the integrated memory package. These intermediaries handle the protocol conversion between the host interface and the different memory interfaces for volatile and non-volatile memories, simplifying the overall architecture by centralizing the complexity in dedicated conversion modules rather than requiring complex integrated solutions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250094081A1Semiconductor memory device
Publication Date: 2025.03.20 SK HYNIX INC
  • US20250094081A1 patent drawing
  • US20250094081A1 patent drawing
  • US20250094081A1 patent drawing

AI summary

The present disclosure relates to a semiconductor memory device including various types of memories to which a host is connected. The semiconductor memory device in one implementation includes a storage memory comprising a nonvolatile memory and a nonvolatile memory controller configured to control the nonvolatile memory; a main memory comprising a volatile memory and a volatile memory controller configured to control the volatile memory; and an access controller communicatively coupled to the storage memory and the main memory and configured to perform data communication with an external device based on a first protocol, perform data communication with the storage memory based on a second protocol, perform data communication with the main memory based on a third protocol, and control access from the external device to the storage memory and the main memory.