Semiconductor Memory Device Uniform Erase Speed Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving uniform erase speeds across multiple memory cell strings, leading to inefficiencies during erase operations.
Innovation Solution
The semiconductor memory device incorporates a voltage supply circuit, a pass circuit, and control logic to apply specific operating voltages and erase voltages to global and local drain select lines, source select lines, and word lines, ensuring uniform erase speeds by managing the timing and potential differences of these voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the same voltage is applied to all global drain select lines simultaneously, then the circuit operation is simple, but the erase speeds of different memory cell strings become non-uniform
Solution Approach 1:
The patent segments the global drain select lines into multiple groups, where each group is controlled by a separate voltage supply circuit. This allows different voltage levels to be applied to different groups of memory cell strings, enabling uniform erase speeds across all strings despite their different positions in the array. The segmentation resolves the contradiction by trading increased circuit complexity for improved erase uniformity.
Solution Approach 2:
The patent applies local quality by providing different voltage levels to different regions or groups of memory cell strings based on their specific characteristics and positions. Each group of global drain select lines receives a tailored voltage level that compensates for position-dependent variations, ensuring uniform erase performance across the entire memory array while accepting the complexity of multiple voltage supply circuits.
2Speed
If higher voltage is applied to all global drain select lines, then the erase operation is faster, but the risk of damage to memory cells increases
Solution Approach 1:
The patent changes the voltage parameter by applying different voltage levels to different groups of global drain select lines. Instead of using a single high voltage for all lines, the system adjusts voltage levels locally to achieve effective erase speeds while maintaining memory cell integrity. This resolves the contradiction by optimizing the voltage parameter for both speed and reliability through localized control.
Data Source
AI summary
Provided herein is a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory block including memory cell strings, a voltage supply circuit configured to apply operating voltages to global drain select lines, global source select lines, and global word lines, and apply an erase voltage to bit lines or to the bit lines and a source line during an erase operation, a pass circuit configured to couple the global drain select lines, global source select lines, and global word lines to local drain select lines, local source select lines, and local word lines in response to a block select signal, and control logic configured to control the voltage supply circuit to apply a first operating voltage to the global drain select lines and thereafter apply a second operating voltage to the global drain select lines.