Memory Device Validation via Mutual Microcode Testing
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Solution Overview
Problem
Semiconductor-based volatile memory devices with embedded memory components pose a challenge for testing, as these components are often hard-wired onto a chip and cannot be tested externally, necessitating a robust built-in self-testing process.
Innovation Solution
A method and system for validating memory devices using microcode instructions stored in validated parts of memory devices, where one memory device validates another based on received microcode instructions, and then validates itself using instructions from the second device, employing both hard-wired and configurable Memory Built-in Self-Test (MBIST) systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external testing is used for memory devices, then testing accuracy is improved, but embedded memory components cannot be tested since they are hard-wired onto the chip
Solution Approach 1:
The patent implements a built-in self-testing process where the memory device tests itself using internal resources. The testing system includes a processor and memory that execute test algorithms internally, eliminating the need for external testing equipment to access embedded memory components that are hard-wired onto the chip.
Solution Approach 2:
The testing system is designed to validate multiple memory devices (first memory device and second memory device) using the same internal testing mechanism. The system can test both the operational status and data integrity of different memory components through a unified built-in testing framework.
2Adaptability or versatility
If built-in self-testing is implemented for embedded memory, then testability of embedded components is improved, but additional internal testing resources increase device complexity
Solution Approach 1:
The patent merges the testing functionality with the existing memory structure by utilizing the memory device's own processor and memory resources to perform validation. The testing system is integrated into the memory device itself, combining storage and testing functions in a unified architecture rather than adding separate external testing components.
Solution Approach 2:
The patent introduces a testing system with a processor and memory that acts as an intermediary between the embedded memory components and the validation process. This intermediary testing mechanism enables comprehensive testing of hard-wired components without requiring external equipment, bridging the gap between embedded memory and test capabilities.
3Reliability
If mutual validation between first and second memory devices is performed, then validation robustness is improved, but validation time increases due to sequential testing
Solution Approach 1:
The patent performs preliminary validation of the first memory device before using it to validate the second memory device. By establishing the reliability of the first memory device in advance, the system creates a trusted reference for subsequent validation, ensuring that the validation process itself is trustworthy while maintaining efficiency.
Solution Approach 2:
The patent implements a feedback mechanism where the validation results from the first memory device are used to inform and guide the validation of the second memory device. The testing system uses the operational status and validation outcomes to adjust and optimize the validation process, improving overall efficiency while maintaining robustness.
Data Source
AI summary
The present invention relates to a method of validating a memory device. The method includes validating a second memory device based on one or more first microcode instructions stored in a validated predetermined part of a first memory device to detect the operational status of the second memory device. Further, the method includes receiving one or more second microcode instructions upon validating the second memory device. Finally, validating the first memory device based on the one or more second microcode instructions stored in the second memory device to detect the operational status of the first memory device.