Memory Device Variable Burst Address Gap Matrix Access
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Solution Overview
Problem
Existing memory devices struggle to efficiently store and read matrices, particularly during AI training operations, due to limitations in storing both original and transposed matrices within limited storage capacity.
Innovation Solution
A memory device and semiconductor system that include a memory cell array and a peripheral circuit, capable of performing a burst operation with a variable burst address gap. This allows for efficient storage and reading of matrices by supporting different burst lengths and address gaps, enabling parallel data transfer and efficient line mapping operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a memory device uses a fixed burst address gap for data transfer, then the control circuit is simple, but the adaptability for different matrix storage and reading operations is limited
Solution Approach 1:
The patent implements a dynamic burst address gap mechanism where the control circuit can change the address gap value based on different operation modes (e.g., row-major or column-major matrix access patterns). This allows the same hardware to adapt to various data transfer requirements without requiring separate dedicated circuits for each mode, thus improving versatility while managing complexity through programmability rather than hardware multiplication.
Solution Approach 2:
The invention changes the address gap parameter dynamically based on the required matrix operation. By allowing the burst address gap to be configurable rather than fixed, the system can optimize data access patterns for different AI training workloads. The control circuit adjusts this parameter based on operation type, enabling efficient storage and reading of matrices with varying dimensional requirements.
2Productivity
If the memory device stores both original and transposed matrices, then the reading speed for AI training is improved, but the storage capacity requirement increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring the memory device with the capability to store matrices in both original and transposed forms during the programming phase. The control circuit is designed to automatically determine the optimal storage layout based on the AI training workload characteristics. This preliminary preparation allows for rapid reading operations during execution without requiring additional real-time processing, thus improving productivity while managing storage requirements through intelligent layout selection.
Solution Approach 2:
The memory device is designed with multi-functionality to handle both original matrix storage and transposed matrix storage using the same physical memory structure. By making the storage system universal rather than requiring separate dedicated storage areas, the device can serve multiple access patterns (row-major and column-major) without proportionally increasing storage capacity. This is achieved through flexible address mapping and burst operation mechanisms that can be configured for different matrix orientations.
3Speed
If the memory device performs sequential data transfer, then the control circuit is simple, but the operation speed is reduced
Solution Approach 1:
The patent implements continuous data transfer through burst operations where multiple data words are transferred in a continuous sequence without interruption. The control circuit manages this by generating continuous address increment signals that maintain the data transfer process without requiring frequent pauses or complex handshaking protocols. This continuous action approach improves data transfer speed while keeping the control circuit relatively simple by avoiding the complexity of interrupt handling and sequential protocol management.
Solution Approach 2:
The control circuit performs preliminary actions by pre-calculating and pre-loading the burst address sequence before the actual data transfer begins. This allows the data transfer to proceed at high speed without frequent control interventions. The control circuit prepares the address generation logic in advance based on the burst length and address gap parameters, enabling rapid sequential access while maintaining simple control architecture through advance preparation rather than complex real-time coordination.
Data Source
AI summary
A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.