Semiconductor Memory Variable Resistance Layer Sidewall Contact
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration and efficiency while reducing processing difficulties, particularly in storing data and switching between resistance states based on voltage or current levels.
Innovation Solution
The proposed solution involves a semiconductor memory device with a substrate having conductive lines in horizontal layers, an insulating layer filling the spaces between them, and a variable resistance layer on the sidewalls of holes etched through these layers, with a conductive pillar filling the holes, allowing for increased integration and efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional memory device structures are used, then processing is simpler, but integration level and contact area are limited
Solution Approach 1:
The patent transitions from planar contact geometry to three-dimensional sidewall contact geometry. The variable resistance layer is formed on the sidewalls of holes etched through multiple insulating layers, creating vertical contact surfaces that significantly increase the contact area between the conductive pillar and the variable resistance layer without increasing the planar footprint.
Solution Approach 2:
The patent implements a nested structure where the variable resistance layer is positioned within the sidewalls of holes that extend through stacked insulating layers. The conductive pillar fills the hole and contacts the variable resistance layer from the interior, creating a nested configuration that maximizes contact area within a compact vertical space.
2Productivity
If more layers are stacked to increase integration, then storage capacity increases, but processing difficulty increases
Solution Approach 1:
The patent divides the memory structure into multiple horizontally stacked layers (first insulating layer, second insulating layer, third insulating layer, etc.) separated by variable resistance layers. Each layer can be processed independently through selective etching, allowing for modular fabrication that scales integration while managing processing complexity through repetitive, standardized steps.
Solution Approach 2:
The patent forms complete holes extending through all insulating layers before depositing the variable resistance material. This preliminary hole formation action simplifies subsequent processing by establishing the three-dimensional contact geometry early, allowing the variable resistance layer to be conformally deposited on pre-formed sidewalls rather than requiring complex simultaneous multi-layer processing.
Data Source
AI summary
An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a substrate having a substantially horizontal upper surface; first to Nth layers (where N is a natural number of two or more) disposed in horizontal layers on the substrate and spaced apart from each other above the substrate in a vertical direction, wherein each of the first to Nth layers includes a plurality of conductive lines; an insulating layer disposed to fill spaces between the conductive lines; a hole having sidewalls that extends in the vertical direction through the conductive lines of the first to Nth layers and the insulating layer therebetween; a variable resistance layer disposed on the sidewalls of the hole; and a conductive pillar disposed to fill the hole in which the variable resistance layer is formed.