Memory-to-Memory Vector Processor for Neural Network Computation
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Solution Overview
Problem
Conventional instruction set architectures for processors are not optimized for vector computations with high instruction repeatability and large data volume, leading to inefficiencies in processing tasks such as neural network computations.
Innovation Solution
A processor architecture with a memory-to-memory (MEM to MEM) design, incorporating an instruction decoder and arithmetic logic unit, which decodes target instructions for vector operations and performs arithmetic logic operations directly in memory, using a simplified instruction set tailored for vector calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional instruction set architectures are used to ensure compatibility with various usage scenarios, then adaptability is improved, but processing efficiency for vector computations deteriorates
Solution Approach 1:
The patent segments the instruction set into two distinct parts: a conventional instruction set for general-purpose computing and a dedicated vector instruction set for high-performance vector computations. This segmentation allows each instruction set to be optimized for its specific purpose, resolving the contradiction between general compatibility and specialized efficiency.
Solution Approach 2:
The processor is designed with multi-functionality by incorporating both conventional and vector instruction sets within a single architecture. The conventional instruction set maintains compatibility with existing software and usage scenarios, while the vector instruction set provides specialized capabilities for high-performance computing, achieving universality across different computational needs.
2Productivity
If a simplified instruction set is designed for vector computations, then processing efficiency is improved, but adaptability to various usage scenarios deteriorates
Solution Approach 1:
The instruction set is segmented into two separate sets: a conventional instruction set that maintains broad compatibility and a dedicated vector instruction set that provides simplified, optimized operations for vector computations. This segmentation allows the simplified vector instructions to achieve high efficiency without compromising the adaptability provided by the conventional instruction set.
Solution Approach 2:
The patent introduces an intermediary mechanism (instruction decoder and dispatcher) that mediates between the two instruction sets. This intermediary component selects and executes the appropriate instruction set based on the computational task, enabling the simplified vector instructions to be used only when beneficial while maintaining overall system adaptability.
3Device complexity
If arithmetic logic operations are performed directly in memory (MEM to MEM), then device complexity is reduced, but operation speed deteriorates
Solution Approach 1:
The patent transitions from traditional register-based processing to memory-based processing by introducing a new dimension of operation. Instead of loading data into registers and performing operations there, the system performs arithmetic logic operations directly in memory using specialized vector instructions, thereby reducing architectural complexity while maintaining performance through optimized memory access patterns.
Data Source
AI summary
A processor and a method, device and storage medium for data processing are provided. The processor includes an instruction decoder configured to decode a target instruction for a vector operation. The target instruction involves a target opcode, a source operand, and a target operand. The target opcode indicates a vector operation specified by the target instruction. The source operand specifies a source storage location in the memory for reading to-be-processed data. The target operand specifies a target storage location in the memory for writing a processed result. The processor further includes an arithmetic logic unit configured to: read the to-be-processed data from the source storage location of the memory; perform, on the to-be-processed data, an arithmetic logic operation associated with the vector operation specified by the target instruction; and write the processed result to the target storage location of the memory.