Nonvolatile Memory Verification Circuit Reducing Common Source Line Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices experience malfunctions due to noise voltage on the common source line, leading to incorrect programming and verification of memory cells, which can result in data being read as non-programmed despite being intended to be programmed.
Innovation Solution
A method and device for programming nonvolatile memory cells that involves selective and sequential verification steps, where bit lines are precharged based on programmed states, reducing the number of ON cells during verification to minimize noise voltage on the common source line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If verification is performed on all memory cells simultaneously, then verification speed is improved, but noise voltage on the common source line increases causing malfunction
Solution Approach 1:
The verification process is divided into multiple sequential stages, each verifying a subset of memory cells. The verification operation is segmented into first verification (initial check), second verification (re-verification of failed cells), and third verification (final check), rather than attempting to verify all cells simultaneously. This segmentation reduces the number of cells verified at any given moment, thereby reducing noise voltage on the common source line while still achieving complete verification coverage.
Solution Approach 2:
The verification is performed in periodic cycles with repeated attempts. Cells that fail verification are re-verified in subsequent cycles. This periodic action allows the system to maintain lower verification intensity in each cycle (reducing noise) while achieving reliable verification through multiple passes, particularly for cells that may be marginally programmed.
2Manufacturing precision
If all memory cells are verified in each programming cycle, then programming accuracy is improved, but operation time increases
Solution Approach 1:
The verification process is divided into multiple sequential stages, each verifying a subset of memory cells. The verification operation is segmented into first verification (initial check), second verification (re-verification of failed cells), and third verification (final check), rather than attempting to verify all cells simultaneously. This segmentation reduces the number of cells verified at any given moment, thereby reducing noise voltage on the common source line while still achieving complete verification coverage.
Solution Approach 2:
The verification is performed in periodic cycles with repeated attempts. Cells that fail verification are re-verified in subsequent cycles. This periodic action allows the system to maintain lower verification intensity in each cycle (reducing noise) while achieving reliable verification through multiple passes, particularly for cells that may be marginally programmed.
Data Source
AI summary
A nonvolatile memory device and a programming method thereof perform a programming verification step including a selective verification step and a sequential verification step. In the selective verification step, a data input/output (I/O) circuit selectively precharges a selected bit line according to a temporary programmed state of stored data. In the sequential verification step, the data I/O circuit selectively precharges each bit line according to the result of the previous selective verification step or a previous sequential verification step. According to the programming method, because a memory cell not requiring a programming verification step is not precharged in the programming verification step, an ON cell current does not flow therethrough. Accordingly, the current flowing through a common source line during verification can be reduced.