Non-Volatile Memory Verification via Common Source Voltage Inversion
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Solution Overview
Problem
The increasing integration of multi-level cells (MLCs) in flash memory devices leads to a significant increase in the number of program verification operations, resulting in longer verification times as the number of bits stored in a memory cell increases, due to the need for multiple verification operations for each program pulse.
Innovation Solution
A method for operating a non-volatile memory device where the state of a sensing node is inverted and latched during data programming and verification in MLCs, allowing data to be stored and transferred through a page buffer by precharging bit lines to a positive voltage and using a common source line to input this voltage, thereby reducing the need for additional circuit changes and enabling efficient data storage and verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cells (MLCs) are used to increase integration degree, then data storage capacity is improved, but the number of program verification operations increases
Solution Approach 1:
The patent inverts the traditional sensing node voltage behavior by applying a positive voltage to the common source line during verification. This causes the sensing node voltage to increase for erased cells and decrease for programmed cells, reversing the conventional response pattern. This inversion enables simplified verification logic for MLCs while maintaining high storage capacity
Solution Approach 2:
The patent changes the voltage parameter applied to the common source line from its conventional negative or zero state to a positive voltage during verification operations. This parameter change fundamentally alters the sensing mechanism, enabling efficient verification of multiple threshold voltage levels in MLCs without increasing the number of verification steps
2Measurement precision
If the number of verification operations is increased to verify MLC states, then measurement precision is improved, but time consumption is increased
Solution Approach 1:
By changing the common source line voltage to positive during verification, the patent enables single-step verification that accurately distinguishes between multiple MLC states (erased, partially programmed, fully programmed) without requiring multiple sequential verification operations, thus maintaining high measurement precision while reducing verification time
3Adaptability or versatility
If conventional verification methods are used for MLCs, then device compatibility is maintained, but verification efficiency is reduced
Solution Approach 1:
The patent modifies the voltage parameter (applying positive voltage to common source line) to create an improved verification method that maintains compatibility with existing MLC structures while dramatically improving verification efficiency through reduced operation cycles and simplified sensing logic
Data Source
AI summary
In a method of operating a non-volatile memory device, a bit line is precharged to a positive voltage, which is input through a common source line of cell strings of memory cells, according to a degree in which a selected memory cell has been programmed. Data according to a voltage level of a sensing node, which is changed according to a level of the voltage of the bit line, is stored in a first latch of a page buffer. The data stored in the first latch is transferred to a second latch through the sensing node.