Non-volatile Memory Verification Circuit for Suspectedly Qualified Bit Detection
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Solution Overview
Problem
Conventional NAND flash memory programming verification circuits are unable to determine if memory cells are suspectedly qualified, leading to reduced programming efficiency and increased errors due to their inability to differentiate between qualified and unqualified bits.
Innovation Solution
A non-volatile semiconductor storage device with a determination circuit that compares detection voltages with reference voltages to determine the permissible number of unqualified bits, allowing for suspectedly qualified bit determination and reducing programming failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional verification circuits determine all bits as qualified or unqualified, then the circuit structure is simple, but the programming efficiency is reduced and yield rate decreases
Solution Approach 1:
The verification circuit is segmented into multiple parallel verification paths, each handling a subset of bits. The determination circuit divides the page into multiple sections and performs verification on each section independently, allowing parallel processing of verification operations which significantly improves programming efficiency while maintaining manageable circuit complexity through modular design
Solution Approach 2:
The invention implements partial verification by checking only a predetermined number of bits in each verification operation rather than all bits. The determination circuit performs verification on limited sections of the page and uses counting logic to track the number of unqualified bits, allowing the system to accept pages with up to a threshold number of errors without performing complete verification on all bits
2Reliability
If all bits are verified to be qualified, then the data quality is high, but the programming time and number of pulses increase
Solution Approach 1:
The determination circuit performs preliminary verification on a predetermined number of bits before final acceptance. By checking limited sections first and using counting logic to track unqualified bits, the system can quickly identify obviously defective pages while allowing pages with minor errors to pass through to ECC correction, reducing unnecessary re-programming cycles and time loss
Solution Approach 2:
The verification circuit implements feedback through the counting logic that tracks the number of unqualified bits. The determination circuit receives verification results and compares the count of unqualified bits against a predetermined threshold, providing feedback that determines whether to accept or reject the page. This feedback mechanism ensures data quality by only accepting pages within error tolerance while avoiding excessive verification time
3Measurement precision
If the verification circuit checks all bits thoroughly, then the error detection capability is high, but the circuit complexity and processing overhead increase
Solution Approach 1:
The verification process is segmented into multiple independent sections, each verified by dedicated verification circuits. The determination circuit divides the page into multiple sections and performs verification on each section independently, allowing parallel processing that maintains high error detection capability while distributing circuit complexity across multiple simpler parallel units rather than one complex sequential unit
Solution Approach 2:
The invention replaces complex mechanical verification mechanisms with electronic counting and comparison logic. The determination circuit uses digital counters to track unqualified bits and comparators to compare counts against thresholds, substituting complex verification mechanics with simpler electronic logic operations that achieve the same error detection function with reduced circuit complexity
Data Source
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AI summary
A non-volatile semiconductor memory device is provided. A determination circuit 200 used to determine the suspectedly qualified is connected with a plurality of page buffer/sensing circuits 170 via wirings PB_UP, PB_MG, PB_DIS. The page buffer/sensing circuit 170 includes a transistor Q2 in which a reference current Iref flows through a transistor Q1 when the programming verification is unqualified. The determination circuit 200 includes a comparator CMP, a voltage of the wiring PB_UP is supplied to one of input terminals of the comparator CMP, and a reference voltage Vref is supplied to another one of the input terminals. The reference voltage Vref is generated by a reference current (Iref*N) whose amount is corresponding to an unqualified bit number (N) which is determined to be suspectedly qualified.